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Commit fcca7926 authored by Ben Widawsky's avatar Ben Widawsky Committed by Keith Packard
Browse files

drm/i915: reference counted forcewake 



Provide a reference count to track the forcewake state of the GPU and
give a safe mechanism for userspace to wake the GT. This also potentially
saves a UC read if the GT is known to be awake already.

The reference count is atomic, but the register access and hardware wake
sequence is protected by struct_mutex.

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent b7287d80

drivers/gpu/drm/i915/i915_debugfs.c

+2 −2
Original line number Diff line number Diff line
@@ -874,7 +874,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
		int max_freq;



		/* RPSTAT1 is in the GT power well */

		__gen6_gt_force_wake_get(dev_priv);

		gen6_gt_force_wake_get(dev_priv);



		rpstat = I915_READ(GEN6_RPSTAT1);

		rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
@@ -919,7 +919,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",

			   max_freq * 50);



		__gen6_gt_force_wake_put(dev_priv);

		gen6_gt_force_wake_put(dev_priv);

	} else {

		seq_printf(m, "no P-state info available\n");

	}

drivers/gpu/drm/i915/i915_drv.c

+28 −2
Original line number Diff line number Diff line
@@ -263,7 +263,7 @@ void intel_detect_pch (struct drm_device *dev) 
	}

}



void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)

static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)

{

	int count;
@@ -279,12 +279,38 @@ void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 
		udelay(10);

}



void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)

/*

 * Generally this is called implicitly by the register read function. However,

 * if some sequence requires the GT to not power down then this function should

 * be called at the beginning of the sequence followed by a call to

 * gen6_gt_force_wake_put() at the end of the sequence.

 */

void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)

{

	WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));



	/* Forcewake is atomic in case we get in here without the lock */

	if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)

		__gen6_gt_force_wake_get(dev_priv);

}



static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)

{

	I915_WRITE_NOTRACE(FORCEWAKE, 0);

	POSTING_READ(FORCEWAKE);

}



/*

 * see gen6_gt_force_wake_get()

 */

void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)

{

	WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));



	if (atomic_dec_and_test(&dev_priv->forcewake_count))

		__gen6_gt_force_wake_put(dev_priv);

}



void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)

{

	int loop = 500;

drivers/gpu/drm/i915/i915_drv.h

+7 −4
Original line number Diff line number Diff line
@@ -709,6 +709,8 @@ typedef struct drm_i915_private { 
	struct intel_fbdev *fbdev;



	struct drm_property *broadcast_rgb_property;



	atomic_t forcewake_count;

} drm_i915_private_t;



enum i915_cache_level {
@@ -1329,8 +1331,8 @@ extern void intel_display_print_error_state(struct seq_file *m, 
 * must be set to prevent GT core from power down and stale values being

 * returned.

 */

void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);

void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);

void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);

void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);

void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);



/* We give fast paths for the really cool registers */
@@ -1343,15 +1345,16 @@ void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 
static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \

	u##x val = 0; \

	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \

		__gen6_gt_force_wake_get(dev_priv); \

		gen6_gt_force_wake_get(dev_priv); \

		val = read##y(dev_priv->regs + reg); \

		__gen6_gt_force_wake_put(dev_priv); \

		gen6_gt_force_wake_put(dev_priv); \

	} else { \

		val = read##y(dev_priv->regs + reg); \

	} \

	trace_i915_reg_rw(false, reg, val, sizeof(val)); \

	return val; \

}



__i915_read(8, b)

__i915_read(16, w)

__i915_read(32, l)

drivers/gpu/drm/i915/i915_irq.c

+0 −1
Original line number Diff line number Diff line
@@ -396,7 +396,6 @@ static void gen6_pm_irq_handler(struct drm_device *dev) 
			I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,

				   I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);

		}



	}



	gen6_set_rps(dev, new_delay);

drivers/gpu/drm/i915/intel_display.c

+4 −4
Original line number Diff line number Diff line
@@ -1540,7 +1540,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev) 
	u32 blt_ecoskpd;



	/* Make sure blitter notifies FBC of writes */

	__gen6_gt_force_wake_get(dev_priv);

	gen6_gt_force_wake_get(dev_priv);

	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);

	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<

		GEN6_BLITTER_LOCK_SHIFT;
@@ -1551,7 +1551,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev) 
			 GEN6_BLITTER_LOCK_SHIFT);

	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);

	POSTING_READ(GEN6_BLITTER_ECOSKPD);

	__gen6_gt_force_wake_put(dev_priv);

	gen6_gt_force_wake_put(dev_priv);

}



static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
@@ -6973,7 +6973,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) 
	 * userspace...

	 */

	I915_WRITE(GEN6_RC_STATE, 0);

	__gen6_gt_force_wake_get(dev_priv);

	gen6_gt_force_wake_get(dev_priv);



	/* disable the counters and set deterministic thresholds */

	I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -7074,7 +7074,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) 
	/* enable all PM interrupts */

	I915_WRITE(GEN6_PMINTRMSK, 0);



	__gen6_gt_force_wake_put(dev_priv);

	gen6_gt_force_wake_put(dev_priv);

}



void intel_enable_clock_gating(struct drm_device *dev)