Loading drivers/power/qpnp-fg.c +14 −0 Original line number Diff line number Diff line Loading @@ -6266,6 +6266,20 @@ static int fg_common_hw_init(struct fg_chip *chip) if (fg_debug_mask & FG_STATUS) pr_info("imptr_pulse_slow is %sabled\n", chip->imptr_pulse_slow_en ? "en" : "dis"); rc = fg_mem_read(chip, &val, RSLOW_CFG_REG, 1, RSLOW_CFG_OFFSET, 0); if (rc) { pr_err("unable to read rslow cfg: %d\n", rc); return rc; } if (val & RSLOW_CFG_ON_VAL) chip->rslow_comp.active = true; if (fg_debug_mask & FG_STATUS) pr_info("rslow_comp active is %sabled\n", chip->rslow_comp.active ? "en" : "dis"); } return 0; Loading Loading
drivers/power/qpnp-fg.c +14 −0 Original line number Diff line number Diff line Loading @@ -6266,6 +6266,20 @@ static int fg_common_hw_init(struct fg_chip *chip) if (fg_debug_mask & FG_STATUS) pr_info("imptr_pulse_slow is %sabled\n", chip->imptr_pulse_slow_en ? "en" : "dis"); rc = fg_mem_read(chip, &val, RSLOW_CFG_REG, 1, RSLOW_CFG_OFFSET, 0); if (rc) { pr_err("unable to read rslow cfg: %d\n", rc); return rc; } if (val & RSLOW_CFG_ON_VAL) chip->rslow_comp.active = true; if (fg_debug_mask & FG_STATUS) pr_info("rslow_comp active is %sabled\n", chip->rslow_comp.active ? "en" : "dis"); } return 0; Loading