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Commit fc6c084b authored by Oleg Perelet's avatar Oleg Perelet
Browse files

msm: kgsl: Change GPU RAC hardware clockgating 



On A5xx disable LRZ clockgating, by setting 0x0
for bits 18:16 of RBBM_CLOCK_CNTL2_RAC.

CRs-Fixed: 964234
Change-Id: Icf858e3431e1c7f9943762067a74b1ce2af7ca6f
Signed-off-by: default avatarOleg Perelet <operelet@codeaurora.org>
parent 99d7b718

drivers/gpu/msm/adreno_a5xx.c

+4 −4
Original line number Diff line number Diff line
@@ -909,7 +909,7 @@ static const struct kgsl_hwcg_reg a50x_hwcg_regs[] = { 
	{A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},

	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},

	{A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},
@@ -966,7 +966,7 @@ static const struct kgsl_hwcg_reg a510_hwcg_regs[] = { 
	{A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
@@ -1057,7 +1057,7 @@ static const struct kgsl_hwcg_reg a530_hwcg_regs[] = { 
	{A5XX_RBBM_CLOCK_CNTL_CCU2, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU3, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU2, 0x04040404},
@@ -1153,7 +1153,7 @@ static const struct kgsl_hwcg_reg a540_hwcg_regs[] = { 
	{A5XX_RBBM_CLOCK_CNTL_CCU2, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_CCU3, 0x00022220},

	{A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00555555},

	{A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},

	{A5XX_RBBM_CLOCK_HYST_RB_CCU2, 0x04040404},