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Commit fc4033b2 authored by Kumar Gala's avatar Kumar Gala
Browse files

powerpc/85xx: add DOZE/NAP support for e500 core 



The e500 core enter DOZE/NAP power-saving modes when the core go to
cpu_idle routine.

The power management default running mode is DOZE, If the user

echo 1 > /proc/sys/kernel/powersave-nap

the system will change to NAP running mode.

Signed-off-by: default avatarDave Liu <daveliu@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 3dfa8773

arch/powerpc/kernel/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ obj-$(CONFIG_IBMVIO) += vio.o 
obj-$(CONFIG_IBMEBUS)           += ibmebus.o

obj-$(CONFIG_GENERIC_TBSYNC)	+= smp-tbsync.o

obj-$(CONFIG_CRASH_DUMP)	+= crash_dump.o

obj-$(CONFIG_E500)		+= idle_e500.o

obj-$(CONFIG_6xx)		+= idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o

obj-$(CONFIG_TAU)		+= tau_6xx.o

obj-$(CONFIG_HIBERNATION)	+= swsusp.o suspend.o \

arch/powerpc/kernel/cputable.c

+0 −3
Original line number Diff line number Diff line
@@ -1491,7 +1491,6 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.pvr_mask		= 0xffff0000,

		.pvr_value		= 0x80200000,

		.cpu_name		= "e500",

		/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */

		.cpu_features		= CPU_FTRS_E500,

		.cpu_user_features	= COMMON_USER_BOOKE |

			PPC_FEATURE_HAS_SPE_COMP |
@@ -1508,7 +1507,6 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.pvr_mask		= 0xffff0000,

		.pvr_value		= 0x80210000,

		.cpu_name		= "e500v2",

		/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */

		.cpu_features		= CPU_FTRS_E500_2,

		.cpu_user_features	= COMMON_USER_BOOKE |

			PPC_FEATURE_HAS_SPE_COMP |
@@ -1526,7 +1524,6 @@ static struct cpu_spec __initdata cpu_specs[] = { 
		.pvr_mask		= 0xffff0000,

		.pvr_value		= 0x80230000,

		.cpu_name		= "e500mc",

		/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */

		.cpu_features		= CPU_FTRS_E500MC,

		.cpu_user_features	= COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,

		.icache_bsize		= 64,

arch/powerpc/kernel/entry_32.S

+4 −4
Original line number Diff line number Diff line
@@ -176,14 +176,14 @@ transfer_to_handler: 
	cmplw	r1,r9			/* if r1 <= ksp_limit */

	ble-	stack_ovf		/* then the kernel stack overflowed */

5:

#ifdef CONFIG_6xx

#if defined(CONFIG_6xx) || defined(CONFIG_E500)

	rlwinm	r9,r1,0,0,31-THREAD_SHIFT

	tophys(r9,r9)			/* check local flags */

	lwz	r12,TI_LOCAL_FLAGS(r9)

	mtcrf	0x01,r12

	bt-	31-TLF_NAPPING,4f

	bt-	31-TLF_SLEEPING,7f

#endif /* CONFIG_6xx */

#endif /* CONFIG_6xx || CONFIG_E500 */

	.globl transfer_to_handler_cont

transfer_to_handler_cont:

3:
@@ -196,10 +196,10 @@ transfer_to_handler_cont: 
	SYNC

	RFI				/* jump to handler, enable MMU */



#ifdef CONFIG_6xx

#if defined (CONFIG_6xx) || defined(CONFIG_E500)

4:	rlwinm	r12,r12,0,~_TLF_NAPPING

	stw	r12,TI_LOCAL_FLAGS(r9)

	b	power_save_6xx_restore

	b	power_save_ppc32_restore



7:	rlwinm	r12,r12,0,~_TLF_SLEEPING

	stw	r12,TI_LOCAL_FLAGS(r9)

arch/powerpc/kernel/head_fsl_booke.S

+47 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 
#include <asm/thread_info.h>

#include <asm/ppc_asm.h>

#include <asm/asm-offsets.h>

#include <asm/cache.h>

#include "head_booke.h"



/* As with the other PowerPC ports, it is expected that when code
@@ -1071,6 +1072,52 @@ _GLOBAL(set_context) 
	isync			/* Force context change */

	blr



_GLOBAL(flush_dcache_L1)

	mfspr	r3,SPRN_L1CFG0



	rlwinm	r5,r3,9,3	/* Extract cache block size */

	twlgti	r5,1		/* Only 32 and 64 byte cache blocks

				 * are currently defined.

				 */

	li	r4,32

	subfic	r6,r5,2		/* r6 = log2(1KiB / cache block size) -

				 *      log2(number of ways)

				 */

	slw	r5,r4,r5	/* r5 = cache block size */



	rlwinm	r7,r3,0,0xff	/* Extract number of KiB in the cache */

	mulli	r7,r7,13	/* An 8-way cache will require 13

				 * loads per set.

				 */

	slw	r7,r7,r6



	/* save off HID0 and set DCFA */

	mfspr	r8,SPRN_HID0

	ori	r9,r8,HID0_DCFA@l

	mtspr	SPRN_HID0,r9

	isync



	lis	r4,KERNELBASE@h

	mtctr	r7



1:	lwz	r3,0(r4)	/* Load... */

	add	r4,r4,r5

	bdnz	1b



	msync

	lis	r4,KERNELBASE@h

	mtctr	r7



1:	dcbf	0,r4		/* ...and flush. */

	add	r4,r4,r5

	bdnz	1b

	

	/* restore HID0 */

	mtspr	SPRN_HID0,r8

	isync



	blr



/*

 * We put a few things here that have to be page-aligned. This stuff

 * goes at the beginning of the data segment, which is page-aligned.

arch/powerpc/kernel/idle_6xx.S

+1 −1
Original line number Diff line number Diff line
@@ -153,7 +153,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 
 * address of current.  R11 points to the exception frame (physical

 * address).  We have to preserve r10.

 */

_GLOBAL(power_save_6xx_restore)

_GLOBAL(power_save_ppc32_restore)

	lwz	r9,_LINK(r11)		/* interrupted in ppc6xx_idle: */

	stw	r9,_NIP(r11)		/* make it do a blr */