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Commit fbf911b4 authored by Shiju Mathew's avatar Shiju Mathew
Browse files

adv7481: Update adv7481 driver on MSM8996 



Add support for adv7481 to use CCI i2c interface and to
changes to make it upto date with the A family.

CRs-Fixed: 998927
Change-Id: If1c9104e3e28a78a886ba184a302e8a4085c0bfd
Signed-off-by: default avatarShiju Mathew <shijum@codeaurora.org>
parent b6f7e713

Documentation/devicetree/bindings/arm/msm/adv7481.txt

0 → 100644
+20 −0
Original line number Diff line number Diff line 
ADV7481 chip driver (VIDEO_ADV7481)



VIDEO_ADV7481 is a kernel platform driver that is used for video decoder

and dual mode HDMI/MHL receiver.



The devicetree representation of the VIDEO_ADV7481 block should be:



Required properties



- compatible: "qcom,adv7481"

- qcom,slave-addr: The i2c slave address of adv7481 driver.

- qcom,cci-master: The i2c master id to be used for adv7481 driver.



Example:



	qcom,adv7481@0 {

		compatible = "qcom,adv7481";

		qcom,cci-master = <0>;

		qcom,slave-addr = <0x70>;

	};

drivers/media/i2c/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -28,6 +28,10 @@ obj-$(CONFIG_VIDEO_ADV7343) += adv7343.o 
obj-$(CONFIG_VIDEO_ADV7393) += adv7393.o

obj-$(CONFIG_VIDEO_ADV7604) += adv7604.o

obj-$(CONFIG_VIDEO_ADV7842) += adv7842.o

ccflags-y += -Idrivers/media/platform/msm/camera_v2

ccflags-y += -Idrivers/media/platform/msm/camera_v2/common

ccflags-y += -Idrivers/media/platform/msm/camera_v2/sensor/io

ccflags-y += -Idrivers/media/platform/msm/camera_v2/sensor/cci

obj-$(CONFIG_VIDEO_ADV7481) += adv7481.o

obj-$(CONFIG_VIDEO_AD9389B) += ad9389b.o

obj-$(CONFIG_VIDEO_ADV7511) += adv7511.o

drivers/media/i2c/adv7481.c

+959 −378

File changed.

Preview size limit exceeded, changes collapsed.

drivers/media/i2c/adv7481_reg.h

+274 −160
Original line number Diff line number Diff line 
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -19,6 +19,9 @@ 
#define ADV_REG_GETFIELD(val, field) \

	(((val) & (field##_BMSK)) >> (field##_SHFT))



#define ADV_REG_RSTFIELD(val, field) \

	((val) & ~((field##_BMSK) << (field##_SHFT)))



/* IO Map Registers */

#define IO_REG_MAIN_RST_ADDR			0xFF

#define IO_REG_MAIN_RST_VALUE			0xFF
@@ -62,12 +65,22 @@ 
#define IO_CTRL_CSI4_IN_SEL_SHFT		2



#define IO_PAD_CTRLS_ADDR			0x0E

#define IO_PAD_FILTER_CTRLS_ADDR		0x0F



#define IO_REG_I2C_CFG_ADDR			0xF2

#define IO_REG_I2C_AUTOINC_EN_REG_VALUE		0x01



#define IO_CTRL_MASTER_PWDN_REG_VALUE		0x01



/* Interrupts */

#define IO_HDMI_LVL_INT_CLEAR_1_ADDR		0x69



#define IO_HDMI_LVL_INT_MASKB_1_ADDR		0x6B

#define IO_AVI_INFO_MB1_BMSK			0x0001

#define IO_AVI_INFO_MB1_SHFT			0



#define IO_HDMI_LVL_INT_CLEAR_2_ADDR		0x6E



#define IO_HDMI_LVL_RAW_STATUS_3_ADDR		0x71

#define IO_TMDSPLL_LCK_A_RAW_BMSK		0x0080

#define IO_TMDSPLL_LCK_A_RAW_SHFT		7
@@ -78,10 +91,13 @@ 
#define IO_DE_REGEN_LCK_RAW_BMSK		0x0001

#define IO_DE_REGEN_LCK_RAW_SHFT		0



/* Interrupts */

#define IO_HDMI_LVL_INT_STATUS_3_ADDR		0x72

#define IO_CABLE_DET_A_ST_BMSK			0x0040

#define IO_CABLE_DET_A_ST_SHFT			6

#define IO_V_LOCKED_ST_BMSK			0x0002

#define IO_V_LOCKED_ST_SHFT			1

#define IO_DE_REGEN_LCK_ST_BMSK			0x0001

#define IO_DE_REGEN_LCK_ST_SHFT			0



#define IO_HDMI_LVL_INT_CLEAR_3_ADDR		0x73

#define IO_CABLE_DET_A_CLR_BMSK			0x0040
@@ -94,6 +110,33 @@ 
#define IO_HDMI_LVL_INT_MASKB_3_ADDR		0x75

#define IO_CABLE_DET_A_MB1_BMSK			0x0040

#define IO_CABLE_DET_A_MB1_SHFT			6

#define IO_V_LOCKED_MB1_BMSK			0x0002

#define IO_V_LOCKED_MB1_SHFT			1

#define IO_DE_REGEN_LCK_MB1_BMSK		0x0001

#define IO_DE_REGEN_LCK_MB1_SHFT		0



#define IO_HDMI_EDG_RAW_STATUS_1_ADDR		0x80

#define IO_NEW_AVI_INFO_RAW_BMSK		0x0001

#define IO_NEW_AVI_INFO_RAW_SHFT		0



#define IO_HDMI_EDG_INT_STATUS_1_ADDR		0x81

#define IO_NEW_AVI_INFO_ST_BMSK			0x0001

#define IO_NEW_AVI_INFO_ST_SHFT			0



#define IO_HDMI_EDG_INT_CLEAR_1_ADDR		0x82

#define IO_NEW_AVI_INFO_CLR_BMSK		0x0001

#define IO_NEW_AVI_INFO_CLR_SHFT		0



#define IO_HDMI_EDG_INT2_MASKB_1_ADDR		0x83

#define IO_NEW_AVI_INFO_MB2_BMSK		0x0001

#define IO_NEW_AVI_INFO_MB2_SHFT		0



#define IO_HDMI_EDG_INT_MASKB_1_ADDR		0x84

#define IO_NEW_AVI_INFO_MB1_BMSK		0x0001

#define IO_NEW_AVI_INFO_MB1_SHFT		0



#define IO_HDMI_EDG_INT_CLEAR_2_ADDR		0x87

#define IO_HDMI_EDG_INT_CLEAR_3_ADDR		0x8C



#define IO_REG_PAD_CTRL_1_ADDR			0x1D

#define IO_PDN_INT1_BMSK			0x0080
@@ -108,6 +151,16 @@ 
#define IO_DRV_LLC_PAD_SHFT			2



#define IO_REG_INT_RAW_STATUS_ADDR		0x3F

#define IO_INT_CEC_ST_BMSK			0x0010

#define IO_INT_CEC_ST_SHFT			4

#define IO_INT_HDMI_ST_BMSK			0x0008

#define IO_INT_HDMI_ST_SHFT			3

#define IO_INTRQ3_RAW_BMSK			0x0004

#define IO_INTRQ3_RAW_SHFT			2

#define IO_INTRQ2_RAW_BMSK			0x0002

#define IO_INTRQ2_RAW_SHFT			1

#define IO_INTRQ1_RAW_BMSK			0x0001

#define IO_INTRQ1_RAW_SHFT			0



#define IO_REG_INT1_CONF_ADDR			0x40

#define IO_INTRQ_DUR_SEL_BMSK			0x00C0
@@ -128,7 +181,29 @@ 
#define IO_INTRQ2_OP_SEL_SHFT			0



#define IO_REG_DATAPATH_RAW_STATUS_ADDR		0x43

#define IO_CP_LOCK_CP_RAW_BMSK			0x0080

#define IO_CP_LOCK_CP_RAW_SHFT			7

#define IO_CP_UNLOCK_CP_RAW_BMSK		0x0040

#define IO_CP_UNLOCK_CP_RAW_SHFT		6

#define IO_VMUTE_REQUEST_HDMI_RAW_BMSK		0x0020

#define IO_VMUTE_REQUEST_HDMI_RAW_SHFT		5

#define IO_MPU_STIM_INTRQ_RAW_BMSK		0x0002

#define IO_MPU_STIM_INTRQ_RAW_SHFT		1

#define IO_INT_SD_RAW_BMSK			0x0001

#define IO_INT_SD_RAW_SHFT			0



#define IO_REG_DATAPATH_INT_STATUS_ADDR		0x44

#define IO_CP_LOCK_CP_ST_BMSK			0x0080

#define IO_CP_LOCK_CP_ST_SHFT			7

#define IO_CP_UNLOCK_CP_ST_BMSK			0x0040

#define IO_CP_UNLOCK_CP_ST_SHFT			6

#define IO_VMUTE_REQUEST_HDMI_ST_BMSK		0x0020

#define IO_VMUTE_REQUEST_HDMI_ST_SHFT		5

#define IO_MPU_STIM_INTRQ_ST_BMSK		0x0002

#define IO_MPU_STIM_INTRQ_ST_SHFT		1

#define IO_INT_SD_ST_BMSK			0x0001

#define IO_INT_SD_ST_SHFT			0



#define IO_REG_DATAPATH_INT_CLEAR_ADDR		0x45



#define IO_REG_DATAPATH_INT_MASKB_ADDR		0x47
@@ -143,6 +218,9 @@ 
#define IO_INT_SD_MB1_BMSK			0x0001

#define IO_INT_SD_MB1_SHFT			0



#define IO_REG_CHIP_REV_ID_1_ADDR		0xDF

#define IO_REG_CHIP_REV_ID_2_ADDR		0xE0



/* Offsets */

#define IO_REG_DPLL_ADDR			0xF3

#define IO_REG_CP_ADDR				0xF4
@@ -264,6 +342,42 @@ 
#define HDMI_EDID_A_ENABLE_BMSK			0x0001

#define HDMI_EDID_A_ENABLE_SHFT			0



/* CEC Map Registers */

#define CEC_REG_LOG_ADDR_MASK_ADDR		0x27

#define CEC_REG_LOG_ADDR_MASK2_BMSK		0x0040

#define CEC_REG_LOG_ADDR_MASK2_SHFT		6

#define CEC_REG_LOG_ADDR_MASK1_BMSK		0x0020

#define CEC_REG_LOG_ADDR_MASK1_SHFT		5

#define CEC_REG_LOG_ADDR_MASK0_BMSK		0x0010

#define CEC_REG_LOG_ADDR_MASK0_SHFT		4

#define CEC_REG_ERROR_REPORT_MODE_BMSK		0x0008

#define CEC_REG_ERROR_REPORT_MODE_SHFT		3

#define CEC_REG_ERROR_REPORT_DET_BMSK		0x0004

#define CEC_REG_ERROR_REPORT_DET_SHFT		2

#define CEC_REG_FORCE_NACK_BMSK			0x0002

#define CEC_REG_FORCE_NACK_SHFT			1

#define CEC_REG_FORCE_IGNORE_BMSK		0x0001

#define CEC_REG_FORCE_IGNORE_SHFT		0



#define CEC_REG_LOGICAL_ADDRESS0_1_ADDR		0x28

#define CEC_REG_LOGICAL_ADDRESS1_BMSK		0x00F0

#define CEC_REG_LOGICAL_ADDRESS1_SHFT		4

#define CEC_REG_LOGICAL_ADDRESS0_BMSK		0x000F

#define CEC_REG_LOGICAL_ADDRESS0_SHFT		0



#define CEC_REG_LOGICAL_ADDRESS2_ADDR		0x29

#define CEC_REG_LOGICAL_ADDRESS2_BMSK		0x000F

#define CEC_REG_LOGICAL_ADDRESS2_SHFT		0



#define CEC_REG_CEC_POWER_UP_ADDR		0x2A

#define CEC_REG_CEC_POWER_UP_BMSK		0x0001

#define CEC_REG_CEC_POWER_UP_SHFT		0



#define CEC_REG_CLR_RX_RDY_SFT_RST_ADDR		0x2C

#define CEC_REG_CEC_SOFT_RESET_BMSK		0x0001

#define CEC_REG_CEC_SOFT_RESET_SHFT		0





/* CP Map Registers */

#define CP_REG_CONTRAST				0x3A

#define CP_REG_SATURATION			0x3B