Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux (fbf21849) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/gpu/drm/i915/i915_gem_dmabuf.c

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -85,9 +85,17 @@ static void i915_gem_unmap_dma_buf(struct dma_buf_attachment *attachment,
	struct sg_table *sg,		struct sg_table *sg,
	enum dma_data_direction dir)		enum dma_data_direction dir)
	{		{
			struct drm_i915_gem_object *obj = attachment->dmabuf->priv;

			mutex_lock(&obj->base.dev->struct_mutex);

	dma_unmap_sg(attachment->dev, sg->sgl, sg->nents, dir);		dma_unmap_sg(attachment->dev, sg->sgl, sg->nents, dir);
	sg_free_table(sg);		sg_free_table(sg);
	kfree(sg);		kfree(sg);

			i915_gem_object_unpin_pages(obj);

			mutex_unlock(&obj->base.dev->struct_mutex);
	}		}

	static void i915_gem_dmabuf_release(struct dma_buf *dma_buf)		static void i915_gem_dmabuf_release(struct dma_buf *dma_buf)

drivers/gpu/drm/i915/intel_display.c

+57 −29

Original line number	Original line	Diff line number	Diff line
	@@ -10042,6 +10042,8 @@ struct intel_display_error_state {

	u32 power_well_driver;		u32 power_well_driver;

			int num_transcoders;

	struct intel_cursor_error_state {		struct intel_cursor_error_state {
	u32 control;		u32 control;
	u32 position;		u32 position;
	@@ -10050,16 +10052,7 @@ struct intel_display_error_state {
	} cursor[I915_MAX_PIPES];		} cursor[I915_MAX_PIPES];

	struct intel_pipe_error_state {		struct intel_pipe_error_state {
	enum transcoder cpu_transcoder;
	u32 conf;
	u32 source;		u32 source;

	u32 htotal;
	u32 hblank;
	u32 hsync;
	u32 vtotal;
	u32 vblank;
	u32 vsync;
	} pipe[I915_MAX_PIPES];		} pipe[I915_MAX_PIPES];

	struct intel_plane_error_state {		struct intel_plane_error_state {
	@@ -10071,6 +10064,19 @@ struct intel_display_error_state {
	u32 surface;		u32 surface;
	u32 tile_offset;		u32 tile_offset;
	} plane[I915_MAX_PIPES];		} plane[I915_MAX_PIPES];

			struct intel_transcoder_error_state {
			enum transcoder cpu_transcoder;

			u32 conf;

			u32 htotal;
			u32 hblank;
			u32 hsync;
			u32 vtotal;
			u32 vblank;
			u32 vsync;
			} transcoder[4];
	};		};

	struct intel_display_error_state *		struct intel_display_error_state *
	@@ -10078,9 +10084,17 @@ intel_display_capture_error_state(struct drm_device *dev)
	{		{
	drm_i915_private_t *dev_priv = dev->dev_private;		drm_i915_private_t *dev_priv = dev->dev_private;
	struct intel_display_error_state *error;		struct intel_display_error_state *error;
	enum transcoder cpu_transcoder;		int transcoders[] = {
			TRANSCODER_A,
			TRANSCODER_B,
			TRANSCODER_C,
			TRANSCODER_EDP,
			};
	int i;		int i;

			if (INTEL_INFO(dev)->num_pipes == 0)
			return NULL;

	error = kmalloc(sizeof(*error), GFP_ATOMIC);		error = kmalloc(sizeof(*error), GFP_ATOMIC);
	if (error == NULL)		if (error == NULL)
	return NULL;		return NULL;
	@@ -10089,9 +10103,6 @@ intel_display_capture_error_state(struct drm_device *dev)
	error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);		error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);

	for_each_pipe(i) {		for_each_pipe(i) {
	cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
	error->pipe[i].cpu_transcoder = cpu_transcoder;

	if (INTEL_INFO(dev)->gen <= 6 \|\| IS_VALLEYVIEW(dev)) {		if (INTEL_INFO(dev)->gen <= 6 \|\| IS_VALLEYVIEW(dev)) {
	error->cursor[i].control = I915_READ(CURCNTR(i));		error->cursor[i].control = I915_READ(CURCNTR(i));
	error->cursor[i].position = I915_READ(CURPOS(i));		error->cursor[i].position = I915_READ(CURPOS(i));
	@@ -10115,14 +10126,25 @@ intel_display_capture_error_state(struct drm_device *dev)
	error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));		error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
	}		}

	error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
	error->pipe[i].source = I915_READ(PIPESRC(i));		error->pipe[i].source = I915_READ(PIPESRC(i));
	error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));		}
	error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
	error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));		error->num_transcoders = INTEL_INFO(dev)->num_pipes;
	error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));		if (HAS_DDI(dev_priv->dev))
	error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));		error->num_transcoders++; /* Account for eDP. */
	error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
			for (i = 0; i < error->num_transcoders; i++) {
			enum transcoder cpu_transcoder = transcoders[i];

			error->transcoder[i].cpu_transcoder = cpu_transcoder;

			error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
			error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
			error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
			error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
			error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
			error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
			error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
	}		}

	/* In the code above we read the registers without checking if the power		/* In the code above we read the registers without checking if the power
	@@ -10144,22 +10166,16 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
	{		{
	int i;		int i;

			if (!error)
			return;

	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);		err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
	if (HAS_POWER_WELL(dev))		if (HAS_POWER_WELL(dev))
	err_printf(m, "PWR_WELL_CTL2: %08x\n",		err_printf(m, "PWR_WELL_CTL2: %08x\n",
	error->power_well_driver);		error->power_well_driver);
	for_each_pipe(i) {		for_each_pipe(i) {
	err_printf(m, "Pipe [%d]:\n", i);		err_printf(m, "Pipe [%d]:\n", i);
	err_printf(m, " CPU transcoder: %c\n",
	transcoder_name(error->pipe[i].cpu_transcoder));
	err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
	err_printf(m, " SRC: %08x\n", error->pipe[i].source);		err_printf(m, " SRC: %08x\n", error->pipe[i].source);
	err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
	err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
	err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
	err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
	err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
	err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);

	err_printf(m, "Plane [%d]:\n", i);		err_printf(m, "Plane [%d]:\n", i);
	err_printf(m, " CNTR: %08x\n", error->plane[i].control);		err_printf(m, " CNTR: %08x\n", error->plane[i].control);
	@@ -10180,5 +10196,17 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
	err_printf(m, " POS: %08x\n", error->cursor[i].position);		err_printf(m, " POS: %08x\n", error->cursor[i].position);
	err_printf(m, " BASE: %08x\n", error->cursor[i].base);		err_printf(m, " BASE: %08x\n", error->cursor[i].base);
	}		}

			for (i = 0; i < error->num_transcoders; i++) {
			err_printf(m, " CPU transcoder: %c\n",
			transcoder_name(error->transcoder[i].cpu_transcoder));
			err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
			err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
			err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
			err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
			err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
			err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
			err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
			}
	}		}
	#endif		#endif

drivers/gpu/drm/radeon/radeon.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -2163,7 +2163,7 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
	WREG32(reg, tmp_); \		WREG32(reg, tmp_); \
	} while (0)		} while (0)
	#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)		#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
	#define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)		#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
	#define WREG32_PLL_P(reg, val, mask) \		#define WREG32_PLL_P(reg, val, mask) \
	do { \		do { \
	uint32_t tmp_ = RREG32_PLL(reg); \		uint32_t tmp_ = RREG32_PLL(reg); \

drivers/gpu/drm/radeon/radeon_uvd.c

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -356,6 +356,14 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser p, struct radeon_bo bo,
	return -EINVAL;		return -EINVAL;
	}		}

			if (bo->tbo.sync_obj) {
			r = radeon_fence_wait(bo->tbo.sync_obj, false);
			if (r) {
			DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
			return r;
			}
			}

	r = radeon_bo_kmap(bo, &ptr);		r = radeon_bo_kmap(bo, &ptr);
	if (r) {		if (r) {
	DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);		DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);

drivers/gpu/drm/radeon/rv770.c

+6 −6

Original line number	Original line	Diff line number	Diff line
	@@ -744,10 +744,10 @@ static void rv770_init_golden_registers(struct radeon_device *rdev)
	(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));		(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
	radeon_program_register_sequence(rdev,		radeon_program_register_sequence(rdev,
	rv730_golden_registers,		rv730_golden_registers,
	(const u32)ARRAY_SIZE(rv770_golden_registers));		(const u32)ARRAY_SIZE(rv730_golden_registers));
	radeon_program_register_sequence(rdev,		radeon_program_register_sequence(rdev,
	rv730_mgcg_init,		rv730_mgcg_init,
	(const u32)ARRAY_SIZE(rv770_mgcg_init));		(const u32)ARRAY_SIZE(rv730_mgcg_init));
	break;		break;
	case CHIP_RV710:		case CHIP_RV710:
	radeon_program_register_sequence(rdev,		radeon_program_register_sequence(rdev,
	@@ -758,18 +758,18 @@ static void rv770_init_golden_registers(struct radeon_device *rdev)
	(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));		(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
	radeon_program_register_sequence(rdev,		radeon_program_register_sequence(rdev,
	rv710_golden_registers,		rv710_golden_registers,
	(const u32)ARRAY_SIZE(rv770_golden_registers));		(const u32)ARRAY_SIZE(rv710_golden_registers));
	radeon_program_register_sequence(rdev,		radeon_program_register_sequence(rdev,
	rv710_mgcg_init,		rv710_mgcg_init,
	(const u32)ARRAY_SIZE(rv770_mgcg_init));		(const u32)ARRAY_SIZE(rv710_mgcg_init));
	break;		break;
	case CHIP_RV740:		case CHIP_RV740:
	radeon_program_register_sequence(rdev,		radeon_program_register_sequence(rdev,
	rv740_golden_registers,		rv740_golden_registers,
	(const u32)ARRAY_SIZE(rv770_golden_registers));		(const u32)ARRAY_SIZE(rv740_golden_registers));
	radeon_program_register_sequence(rdev,		radeon_program_register_sequence(rdev,
	rv740_mgcg_init,		rv740_mgcg_init,
	(const u32)ARRAY_SIZE(rv770_mgcg_init));		(const u32)ARRAY_SIZE(rv740_mgcg_init));
	break;		break;
	default:		default:
	break;		break;