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Commit fbeb1f19 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6 

* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6:
  serial: Fix sh-sci break interrupt/sysrq handling.
  sh: Fix bogus regs pointer in do_IRQ().
  sh: Fix SH-3 cache entry_mask and way_size calculation.
  sh: Convert struct ioctls to static defines.
  sh: Define missing __NR_readahead.
  sh: Fix PCI BAR address-space wraparound.
parents 5851fadc 0b3d4ef6

arch/sh/drivers/pci/pci-auto.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -214,6 +214,12 @@ retry: 
			continue;

			continue;

		}

		}





		if (bar_value < *lower_limit || (bar_value + bar_size) >= *upper_limit) {

			DBG(" unavailable -- skipping, value %x size %x\n",

					bar_value, bar_size);

			continue;

		}



#ifdef CONFIG_PCI_AUTO_UPDATE_RESOURCES

#ifdef CONFIG_PCI_AUTO_UPDATE_RESOURCES

		/* Write it out and update our limit */

		/* Write it out and update our limit */

		early_write_config_dword(hose, top_bus, current_bus, pci_devfn,

		early_write_config_dword(hose, top_bus, current_bus, pci_devfn,

arch/sh/kernel/cpu/init.c

+17 −3
Original line number Original line Diff line number Diff line
@@ -3,7 +3,7 @@ 
 *

 *

 * CPU init code

 * CPU init code

 *

 *

 * Copyright (C) 2002 - 2006  Paul Mundt

 * Copyright (C) 2002 - 2007  Paul Mundt

 * Copyright (C) 2003  Richard Curnow

 * Copyright (C) 2003  Richard Curnow

 *

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * This file is subject to the terms and conditions of the GNU General Public
@@ -48,8 +48,19 @@ static void __init cache_init(void) 
{

{

	unsigned long ccr, flags;

	unsigned long ccr, flags;





	if (current_cpu_data.type == CPU_SH_NONE)

	/* First setup the rest of the I-cache info */

		panic("Unknown CPU");

	current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -

				      current_cpu_data.icache.linesz;



	current_cpu_data.icache.way_size = current_cpu_data.icache.sets *

				    current_cpu_data.icache.linesz;



	/* And the D-cache too */

	current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -

				      current_cpu_data.dcache.linesz;



	current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *

				    current_cpu_data.dcache.linesz;





	jump_to_P2();

	jump_to_P2();

	ccr = ctrl_inl(CCR);

	ccr = ctrl_inl(CCR);
@@ -200,6 +211,9 @@ asmlinkage void __init sh_cpu_init(void) 
	/* First, probe the CPU */

	/* First, probe the CPU */

	detect_cpu_and_cache_system();

	detect_cpu_and_cache_system();





	if (current_cpu_data.type == CPU_SH_NONE)

		panic("Unknown CPU");



	/* Init the cache */

	/* Init the cache */

	cache_init();

	cache_init();

arch/sh/kernel/cpu/sh2/entry.S

+1 −0
Original line number Original line Diff line number Diff line
@@ -165,6 +165,7 @@ ENTRY(exception_handler) 




interrupt_entry:

interrupt_entry:

	mov	r9,r4

	mov	r9,r4

	mov	r15,r5

	mov.l	6f,r9

	mov.l	6f,r9

	mov.l	7f,r8

	mov.l	7f,r8

	jmp	@r8

	jmp	@r8

arch/sh/kernel/cpu/sh3/entry.S

+4 −1
Original line number Original line Diff line number Diff line
@@ -514,13 +514,16 @@ skip_save: 




interrupt_exception:

interrupt_exception:

	mov.l	1f, r9

	mov.l	1f, r9

	mov.l	2f, r4

	mov.l	@r4, r4

	jmp	@r9

	jmp	@r9

	 nop

	 mov	r15, r5

	rts

	rts

	 nop

	 nop





	.align 2

	.align 2

1:	.long	do_IRQ

1:	.long	do_IRQ

2:	.long	INTEVT





	.align	2

	.align	2

ENTRY(exception_none)

ENTRY(exception_none)

arch/sh/kernel/cpu/sh4/probe.c

+0 −13
Original line number Original line Diff line number Diff line
@@ -195,13 +195,6 @@ int __init detect_cpu_and_cache_system(void) 




	}

	}





	/* Setup the rest of the I-cache info */

	current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -

				      current_cpu_data.icache.linesz;



	current_cpu_data.icache.way_size = current_cpu_data.icache.sets *

				    current_cpu_data.icache.linesz;



	/* And the rest of the D-cache */

	/* And the rest of the D-cache */

	if (current_cpu_data.dcache.ways > 1) {

	if (current_cpu_data.dcache.ways > 1) {

		size = sizes[(cvr >> 16) & 0xf];

		size = sizes[(cvr >> 16) & 0xf];
@@ -209,12 +202,6 @@ int __init detect_cpu_and_cache_system(void) 
		current_cpu_data.dcache.sets		= (size >> 6);

		current_cpu_data.dcache.sets		= (size >> 6);

	}

	}





	current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -

				      current_cpu_data.dcache.linesz;



	current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *

				    current_cpu_data.dcache.linesz;



	/*

	/*

	 * Setup the L2 cache desc

	 * Setup the L2 cache desc

	 *

	 *