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Commit fad63209 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 

* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
  drm/radeon/nouveau: fix build regression on alpha due to Xen changes.
  drm/radeon/kms: fix cayman acceleration
  drm/radeon: fix cayman struct accessors.
parents b5121290 03a80665

drivers/gpu/drm/nouveau/nouveau_sgdma.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -42,7 +42,8 @@ nouveau_sgdma_populate(struct ttm_backend *be, unsigned long num_pages, 




	nvbe->nr_pages = 0;

	nvbe->nr_pages = 0;

	while (num_pages--) {

	while (num_pages--) {

		if (dma_addrs[nvbe->nr_pages] != DMA_ERROR_CODE) {

		/* this code path isn't called and is incorrect anyways */

		if (0) { /*dma_addrs[nvbe->nr_pages] != DMA_ERROR_CODE)*/

			nvbe->pages[nvbe->nr_pages] =

			nvbe->pages[nvbe->nr_pages] =

					dma_addrs[nvbe->nr_pages];

					dma_addrs[nvbe->nr_pages];

		 	nvbe->ttm_alloced[nvbe->nr_pages] = true;

		 	nvbe->ttm_alloced[nvbe->nr_pages] = true;

drivers/gpu/drm/radeon/ni.c

+9 −9
Original line number Original line Diff line number Diff line
@@ -674,7 +674,7 @@ static void cayman_gpu_init(struct radeon_device *rdev) 




	cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);

	cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);

	cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);

	cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);

	cgts_tcc_disable = RREG32(CGTS_TCC_DISABLE);

	cgts_tcc_disable = 0xff000000;

	gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);

	gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);

	gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);

	gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);

	cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);

	cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
@@ -871,7 +871,7 @@ static void cayman_gpu_init(struct radeon_device *rdev) 




	smx_dc_ctl0 = RREG32(SMX_DC_CTL0);

	smx_dc_ctl0 = RREG32(SMX_DC_CTL0);

	smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);

	smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);

	smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);

	smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);

	WREG32(SMX_DC_CTL0, smx_dc_ctl0);

	WREG32(SMX_DC_CTL0, smx_dc_ctl0);





	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);

	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
@@ -887,20 +887,20 @@ static void cayman_gpu_init(struct radeon_device *rdev) 




	WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);

	WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);





	WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |

	WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |

					POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |

					POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |

					SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));

					SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));





	WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |

	WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |

				 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |

				 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |

				 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));

				 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));









	WREG32(VGT_NUM_INSTANCES, 1);

	WREG32(VGT_NUM_INSTANCES, 1);





	WREG32(CP_PERFMON_CNTL, 0);

	WREG32(CP_PERFMON_CNTL, 0);





	WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |

	WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |

				  FETCH_FIFO_HIWATER(0x4) |

				  FETCH_FIFO_HIWATER(0x4) |

				  DONE_FIFO_HIWATER(0xe0) |

				  DONE_FIFO_HIWATER(0xe0) |

				  ALU_UPDATE_FIFO_HIWATER(0x8)));

				  ALU_UPDATE_FIFO_HIWATER(0x8)));

drivers/gpu/drm/radeon/radeon_gart.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -181,9 +181,9 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 
	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);

	p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);





	for (i = 0; i < pages; i++, p++) {

	for (i = 0; i < pages; i++, p++) {

		/* On TTM path, we only use the DMA API if TTM_PAGE_FLAG_DMA32

		/* we reverted the patch using dma_addr in TTM for now but this

		 * is requested. */

		 * code stops building on alpha so just comment it out for now */

		if (dma_addr[i] != DMA_ERROR_CODE) {

		if (0) { /*dma_addr[i] != DMA_ERROR_CODE) */

			rdev->gart.ttm_alloced[p] = true;

			rdev->gart.ttm_alloced[p] = true;

			rdev->gart.pages_addr[p] = dma_addr[i];

			rdev->gart.pages_addr[p] = dma_addr[i];

		} else {

		} else {