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Commit fab8ad0b authored by Jon Hunter's avatar Jon Hunter Committed by Benoit Cousson
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ARM: dts: OMAP: Add timer nodes 



Add the 12 GP timers nodes present in OMAP2.
Add the 12 GP timers nodes present in OMAP3.
Add the 11 GP timers nodes present in OMAP4.
Add the 7 GP timers nodes present in AM33xx.

Add documentation for timer properties specific to OMAP.

Thanks to Vaibhav Hiremath for creating the AM33xx timer nodes. I have modified
Vaibhav's original nodes adding information on which timers support a PWM
output.

V5 changes:
- Updated timer register sizes for OMAP2/3/4.
- Modified AM335x timer register size to be 1KB instead of 4KB to align with
  HWMOD.

Signed-off-by: default avatarJon Hunter <jon-hunter@ti.com>
Acked-Reviewed-&-Tested-By: default avatarVaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: default avatarBenoit Cousson <b-cousson@ti.com>
parent 4c94ac29

Documentation/devicetree/bindings/arm/omap/timer.txt

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OMAP Timer bindings



Required properties:

- compatible:		Must be "ti,omap2-timer" for OMAP2+ controllers.

- reg:			Contains timer register address range (base address and

			length).

- interrupts: 		Contains the interrupt information for the timer. The

			format is being dependent on which interrupt controller

			the OMAP device uses.

- ti,hwmods:		Name of the hwmod associated to the timer, "timer<X>",

			where <X> is the instance number of the timer from the

			HW spec.



Optional properties:

- ti,timer-alwon:	Indicates the timer is in an alway-on power domain.

- ti,timer-dsp:		Indicates the timer can interrupt the on-chip DSP in

			addition to the ARM CPU.

- ti,timer-pwm: 	Indicates the timer can generate a PWM output.

- ti,timer-secure: 	Indicates the timer is reserved on a secure OMAP device

			and therefore cannot be used by the kernel.



Example:



timer12: timer@48304000 {

	compatible = "ti,omap2-timer";

	reg = <0x48304000 0x400>;

	interrupts = <95>;

	ti,hwmods = "timer12"

	ti,timer-alwon;

	ti,timer-secure;

};

arch/arm/boot/dts/am33xx.dtsi

+54 −0
Original line number Diff line number Diff line
@@ -237,5 +237,59 @@ 
			interrupts = <55>;

			status = "disabled";

		};



		timer1: timer@44e31000 {

			compatible = "ti,omap2-timer";

			reg = <0x44e31000 0x400>;

			interrupts = <67>;

			ti,hwmods = "timer1";

			ti,timer-alwon;

		};



		timer2: timer@48040000 {

			compatible = "ti,omap2-timer";

			reg = <0x48040000 0x400>;

			interrupts = <68>;

			ti,hwmods = "timer2";

		};



		timer3: timer@48042000 {

			compatible = "ti,omap2-timer";

			reg = <0x48042000 0x400>;

			interrupts = <69>;

			ti,hwmods = "timer3";

		};



		timer4: timer@48044000 {

			compatible = "ti,omap2-timer";

			reg = <0x48044000 0x400>;

			interrupts = <92>;

			ti,hwmods = "timer4";

			ti,timer-pwm;

		};



		timer5: timer@48046000 {

			compatible = "ti,omap2-timer";

			reg = <0x48046000 0x400>;

			interrupts = <93>;

			ti,hwmods = "timer5";

			ti,timer-pwm;

		};



		timer6: timer@48048000 {

			compatible = "ti,omap2-timer";

			reg = <0x48048000 0x400>;

			interrupts = <94>;

			ti,hwmods = "timer6";

			ti,timer-pwm;

		};



		timer7: timer@4804a000 {

			compatible = "ti,omap2-timer";

			reg = <0x4804a000 0x400>;

			interrupts = <95>;

			ti,hwmods = "timer7";

			ti,timer-pwm;

		};

	};

};

arch/arm/boot/dts/omap2.dtsi

+85 −0
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@@ -66,5 +66,90 @@ 
			ti,hwmods = "uart3";

			clock-frequency = <48000000>;

		};



		timer2: timer@4802a000 {

			compatible = "ti,omap2-timer";

			reg = <0x4802a000 0x400>;

			interrupts = <38>;

			ti,hwmods = "timer2";

		};



		timer3: timer@48078000 {

			compatible = "ti,omap2-timer";

			reg = <0x48078000 0x400>;

			interrupts = <39>;

			ti,hwmods = "timer3";

		};



		timer4: timer@4807a000 {

			compatible = "ti,omap2-timer";

			reg = <0x4807a000 0x400>;

			interrupts = <40>;

			ti,hwmods = "timer4";

		};



		timer5: timer@4807c000 {

			compatible = "ti,omap2-timer";

			reg = <0x4807c000 0x400>;

			interrupts = <41>;

			ti,hwmods = "timer5";

			ti,timer-dsp;

		};



		timer6: timer@4807e000 {

			compatible = "ti,omap2-timer";

			reg = <0x4807e000 0x400>;

			interrupts = <42>;

			ti,hwmods = "timer6";

			ti,timer-dsp;

		};



		timer7: timer@48080000 {

			compatible = "ti,omap2-timer";

			reg = <0x48080000 0x400>;

			interrupts = <43>;

			ti,hwmods = "timer7";

			ti,timer-dsp;

		};



		timer8: timer@48082000 {

			compatible = "ti,omap2-timer";

			reg = <0x48082000 0x400>;

			interrupts = <44>;

			ti,hwmods = "timer8";

			ti,timer-dsp;

		};



		timer9: timer@48084000 {

			compatible = "ti,omap2-timer";

			reg = <0x48084000 0x400>;

			interrupts = <45>;

			ti,hwmods = "timer9";

			ti,timer-pwm;

		};



		timer10: timer@48086000 {

			compatible = "ti,omap2-timer";

			reg = <0x48086000 0x400>;

			interrupts = <46>;

			ti,hwmods = "timer10";

			ti,timer-pwm;

		};



		timer11: timer@48088000 {

			compatible = "ti,omap2-timer";

			reg = <0x48088000 0x400>;

			interrupts = <47>;

			ti,hwmods = "timer11";

			ti,timer-pwm;

		};



		timer12: timer@4808a000 {

			compatible = "ti,omap2-timer";

			reg = <0x4808a000 0x400>;

			interrupts = <48>;

			ti,hwmods = "timer12";

			ti,timer-pwm;

		};

	};

};

arch/arm/boot/dts/omap2420.dtsi

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@@ -42,5 +42,13 @@ 
			interrupt-names = "tx", "rx";

			ti,hwmods = "mcbsp2";

		};



		timer1: timer@48028000 {

			compatible = "ti,omap2-timer";

			reg = <0x48028000 0x400>;

			interrupts = <37>;

			ti,hwmods = "timer1";

			ti,timer-alwon;

		};

	};

};

arch/arm/boot/dts/omap2430.dtsi

+8 −0
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@@ -83,5 +83,13 @@ 
			ti,buffer-size = <128>;

			ti,hwmods = "mcbsp5";

		};



		timer1: timer@49018000 {

			compatible = "ti,omap2-timer";

			reg = <0x49018000 0x400>;

			interrupts = <37>;

			ti,hwmods = "timer1";

			ti,timer-alwon;

		};

	};

};