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Commit fa59440d authored by Linus Walleij's avatar Linus Walleij Committed by Russell King
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[ARM] 5470/1: U300 register definitions 



This adds registers, interrupt numbers and IO mappings
for the U300 series platforms core support, including
basic block offsets and registers definitions for the
system controller.

Signed-off-by: default avatarLinus Walleij <linus.walleij@stericsson.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent b4175b89

arch/arm/mach-u300/include/mach/hardware.h

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/*

 * arch/arm/mach-u300/include/mach/hardware.h

 */

#include <asm/sizes.h>

#include <mach/u300-regs.h>

arch/arm/mach-u300/include/mach/io.h

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/*

 *

 * arch/arm/mach-u300/include/mach/io.h

 *

 *

 * Copyright (C) 2006-2009 ST-Ericsson AB

 * License terms: GNU General Public License (GPL) version 2

 * Dummy IO map for being able to use writew()/readw(),

 * writel()/readw() and similar accessor functions.

 * Author: Linus Walleij <linus.walleij@stericsson.com>

 */

#ifndef __MACH_IO_H

#define __MACH_IO_H



#define IO_SPACE_LIMIT 0xffffffff



#define __io(a)		__typesafe_io(a)

#define __mem_pci(a)	(a)



#endif

arch/arm/mach-u300/include/mach/irqs.h

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/*

 *

 * arch/arm/mach-u300/include/mach/irqs.h

 *

 *

 * Copyright (C) 2006-2009 ST-Ericsson AB

 * License terms: GNU General Public License (GPL) version 2

 * IRQ channel definitions for the U300 platforms.

 * Author: Linus Walleij <linus.walleij@stericsson.com>

 */



#ifndef __MACH_IRQS_H

#define __MACH_IRQS_H



#define IRQ_U300_INTCON0_START		0

#define IRQ_U300_INTCON1_START		32

/* These are on INTCON0 - 30 lines */

#define IRQ_U300_IRQ0_EXT		0

#define IRQ_U300_IRQ1_EXT		1

#define IRQ_U300_DMA			2

#define IRQ_U300_VIDEO_ENC_0		3

#define IRQ_U300_VIDEO_ENC_1		4

#define IRQ_U300_AAIF_RX		5

#define IRQ_U300_AAIF_TX		6

#define IRQ_U300_AAIF_VGPIO		7

#define IRQ_U300_AAIF_WAKEUP		8

#define IRQ_U300_PCM_I2S0_FRAME		9

#define IRQ_U300_PCM_I2S0_FIFO		10

#define IRQ_U300_PCM_I2S1_FRAME		11

#define IRQ_U300_PCM_I2S1_FIFO		12

#define IRQ_U300_XGAM_GAMCON		13

#define IRQ_U300_XGAM_CDI		14

#define IRQ_U300_XGAM_CDICON		15

#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)

/* MMIACC not used on the DB3210 or DB3350 chips */

#define IRQ_U300_XGAM_MMIACC		16

#endif

#define IRQ_U300_XGAM_PDI		17

#define IRQ_U300_XGAM_PDICON		18

#define IRQ_U300_XGAM_GAMEACC		19

#define IRQ_U300_XGAM_MCIDCT		20

#define IRQ_U300_APEX			21

#define IRQ_U300_UART0			22

#define IRQ_U300_SPI			23

#define IRQ_U300_TIMER_APP_OS		24

#define IRQ_U300_TIMER_APP_DD		25

#define IRQ_U300_TIMER_APP_GP1		26

#define IRQ_U300_TIMER_APP_GP2		27

#define IRQ_U300_TIMER_OS		28

#define IRQ_U300_TIMER_MS		29

#define IRQ_U300_KEYPAD_KEYBF		30

#define IRQ_U300_KEYPAD_KEYBR		31

/* These are on INTCON1 - 32 lines */

#define IRQ_U300_GPIO_PORT0		32

#define IRQ_U300_GPIO_PORT1		33

#define IRQ_U300_GPIO_PORT2		34



#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \

    defined(CONFIG_MACH_U300_BS335)

/* These are for DB3150, DB3200 and DB3350 */

#define IRQ_U300_WDOG			35

#define IRQ_U300_EVHIST			36

#define IRQ_U300_MSPRO			37

#define IRQ_U300_MMCSD_MCIINTR0		38

#define IRQ_U300_MMCSD_MCIINTR1		39

#define IRQ_U300_I2C0			40

#define IRQ_U300_I2C1			41

#define IRQ_U300_RTC			42

#define IRQ_U300_NFIF			43

#define IRQ_U300_NFIF2			44

#endif



/* DB3150 and DB3200 have only 45 IRQs */

#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)

#define U300_NR_IRQS			45

#endif



/* The DB3350-specific interrupt lines */

#ifdef CONFIG_MACH_U300_BS335

#define IRQ_U300_ISP_F0			45

#define IRQ_U300_ISP_F1			46

#define IRQ_U300_ISP_F2			47

#define IRQ_U300_ISP_F3			48

#define IRQ_U300_ISP_F4			49

#define IRQ_U300_GPIO_PORT3		50

#define IRQ_U300_SYSCON_PLL_LOCK	51

#define IRQ_U300_UART1			52

#define IRQ_U300_GPIO_PORT4		53

#define IRQ_U300_GPIO_PORT5		54

#define IRQ_U300_GPIO_PORT6		55

#define U300_NR_IRQS			56

#endif



/* The DB3210-specific interrupt lines */

#ifdef CONFIG_MACH_U300_BS365

#define IRQ_U300_GPIO_PORT3		35

#define IRQ_U300_GPIO_PORT4		36

#define IRQ_U300_WDOG			37

#define IRQ_U300_EVHIST			38

#define IRQ_U300_MSPRO			39

#define IRQ_U300_MMCSD_MCIINTR0		40

#define IRQ_U300_MMCSD_MCIINTR1		41

#define IRQ_U300_I2C0			42

#define IRQ_U300_I2C1			43

#define IRQ_U300_RTC			44

#define IRQ_U300_NFIF			45

#define IRQ_U300_NFIF2			46

#define IRQ_U300_SYSCON_PLL_LOCK	47

#define U300_NR_IRQS			48

#endif



#define NR_IRQS U300_NR_IRQS



#endif

arch/arm/mach-u300/include/mach/syscon.h

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arch/arm/mach-u300/include/mach/u300-regs.h

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/*

 *

 * arch/arm/mach-u300/include/mach/u300-regs.h

 *

 *

 * Copyright (C) 2006-2009 ST-Ericsson AB

 * License terms: GNU General Public License (GPL) version 2

 * Basic register address definitions in physical memory and

 * some block defintions for core devices like the timer.

 * Author: Linus Walleij <linus.walleij@stericsson.com>

 */



#ifndef __MACH_U300_REGS_H

#define __MACH_U300_REGS_H



/*

 * These are the large blocks of memory allocated for I/O.

 * the defines are used for setting up the I/O memory mapping.

 */



/* NAND Flash CS0 */

#define U300_NAND_CS0_PHYS_BASE		0x80000000

#define U300_NAND_CS0_VIRT_BASE		0xff040000



/* NFIF */

#define U300_NAND_IF_PHYS_BASE		0x9f800000

#define U300_NAND_IF_VIRT_BASE		0xff030000



/* AHB Peripherals */

#define U300_AHB_PER_PHYS_BASE		0xa0000000

#define U300_AHB_PER_VIRT_BASE		0xff010000



/* FAST Peripherals */

#define U300_FAST_PER_PHYS_BASE		0xc0000000

#define U300_FAST_PER_VIRT_BASE		0xff020000



/* SLOW Peripherals */

#define U300_SLOW_PER_PHYS_BASE		0xc0010000

#define U300_SLOW_PER_VIRT_BASE		0xff000000



/* Boot ROM */

#define U300_BOOTROM_PHYS_BASE		0xffff0000

#define U300_BOOTROM_VIRT_BASE		0xffff0000



/* SEMI config base */

#ifdef CONFIG_MACH_U300_BS335

#define U300_SEMI_CONFIG_BASE		0x2FFE0000

#else

#define U300_SEMI_CONFIG_BASE		0x30000000

#endif



/*

 * All the following peripherals are specified at their PHYSICAL address,

 * so if you need to access them (in the kernel), you MUST use the macros

 * defined in <asm/io.h> to map to the IO_ADDRESS_AHB() IO_ADDRESS_FAST()

 * etc.

 */



/*

 * AHB peripherals

 */



/* AHB Peripherals Bridge Controller */

#define U300_AHB_BRIDGE_BASE		(U300_AHB_PER_PHYS_BASE+0x0000)



/* Vectored Interrupt Controller 0, servicing 32 interrupts */

#define U300_INTCON0_BASE		(U300_AHB_PER_PHYS_BASE+0x1000)

#define U300_INTCON0_VBASE		(U300_AHB_PER_VIRT_BASE+0x1000)



/* Vectored Interrupt Controller 1, servicing 32 interrupts */

#define U300_INTCON1_BASE		(U300_AHB_PER_PHYS_BASE+0x2000)

#define U300_INTCON1_VBASE		(U300_AHB_PER_VIRT_BASE+0x2000)



/* Memory Stick Pro (MSPRO) controller */

#define U300_MSPRO_BASE			(U300_AHB_PER_PHYS_BASE+0x3000)



/* EMIF Configuration Area */

#define U300_EMIF_CFG_BASE		(U300_AHB_PER_PHYS_BASE+0x4000)





/*

 * FAST peripherals

 */



/* FAST bridge control */

#define U300_FAST_BRIDGE_BASE		(U300_FAST_PER_PHYS_BASE+0x0000)



/* MMC/SD controller */

#define U300_MMCSD_BASE			(U300_FAST_PER_PHYS_BASE+0x1000)



/* PCM I2S0 controller */

#define U300_PCM_I2S0_BASE		(U300_FAST_PER_PHYS_BASE+0x2000)



/* PCM I2S1 controller */

#define U300_PCM_I2S1_BASE		(U300_FAST_PER_PHYS_BASE+0x3000)



/* I2C0 controller */

#define U300_I2C0_BASE			(U300_FAST_PER_PHYS_BASE+0x4000)



/* I2C1 controller */

#define U300_I2C1_BASE			(U300_FAST_PER_PHYS_BASE+0x5000)



/* SPI controller */

#define U300_SPI_BASE			(U300_FAST_PER_PHYS_BASE+0x6000)



#ifdef CONFIG_MACH_U300_BS335

/* Fast UART1 on U335 only */

#define U300_UART1_BASE			(U300_SLOW_PER_PHYS_BASE+0x7000)

#endif



/*

 * SLOW peripherals

 */



/* SLOW bridge control */

#define U300_SLOW_BRIDGE_BASE		(U300_SLOW_PER_PHYS_BASE)



/* SYSCON */

#define U300_SYSCON_BASE		(U300_SLOW_PER_PHYS_BASE+0x1000)

#define U300_SYSCON_VBASE		(U300_SLOW_PER_VIRT_BASE+0x1000)



/* Watchdog */

#define U300_WDOG_BASE			(U300_SLOW_PER_PHYS_BASE+0x2000)



/* UART0 */

#define U300_UART0_BASE			(U300_SLOW_PER_PHYS_BASE+0x3000)



/* APP side special timer */

#define U300_TIMER_APP_BASE		(U300_SLOW_PER_PHYS_BASE+0x4000)

#define U300_TIMER_APP_VBASE		(U300_SLOW_PER_VIRT_BASE+0x4000)



/* Keypad */

#define U300_KEYPAD_BASE		(U300_SLOW_PER_PHYS_BASE+0x5000)



/* GPIO */

#define U300_GPIO_BASE			(U300_SLOW_PER_PHYS_BASE+0x6000)



/* RTC */

#define U300_RTC_BASE			(U300_SLOW_PER_PHYS_BASE+0x7000)



/* Bus tracer */

#define U300_BUSTR_BASE			(U300_SLOW_PER_PHYS_BASE+0x8000)



/* Event handler (hardware queue) */

#define U300_EVHIST_BASE		(U300_SLOW_PER_PHYS_BASE+0x9000)



/* Genric Timer */

#define U300_TIMER_BASE			(U300_SLOW_PER_PHYS_BASE+0xa000)



/* PPM */

#define U300_PPM_BASE			(U300_SLOW_PER_PHYS_BASE+0xb000)





/*

 * REST peripherals

 */



/* ISP (image signal processor) is only available in U335 */

#ifdef CONFIG_MACH_U300_BS335

#define U300_ISP_BASE			(0xA0008000)

#endif



/* DMA Controller base */

#define U300_DMAC_BASE			(0xC0020000)



/* MSL Base */

#define U300_MSL_BASE			(0xc0022000)



/* APEX Base */

#define U300_APEX_BASE			(0xc0030000)



/* Video Encoder Base */

#ifdef CONFIG_MACH_U300_BS335

#define U300_VIDEOENC_BASE		(0xc0080000)

#else

#define U300_VIDEOENC_BASE		(0xc0040000)

#endif



/* XGAM Base */

#define U300_XGAM_BASE			(0xd0000000)



/*

 * Virtual accessor macros for static devices

 */





#endif