Merge "ARM: dts: msm: support the coexistence of 9x40 and mdmcalifornium" (fa1f37d1) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/boot/dts/qcom/mdm9640-pinctrl.dtsi

+44 −0

Original line number	Diff line number	Diff line
		@@ -325,6 +325,50 @@
		};
		};

		pcie_ep0 {
		/* pcie_ep_clkreq_groups */
		pcie_ep0_clkreq_default: pcie_ep_clkreq_default {
		mux {
		pins = "gpio64";
		function = "pcie_clkreq";
		};

		config {
		pins = "gpio64";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		/* pcie_ep_rst_groups */
		pcie_ep0_perst_default: pcie_ep0_perst_default {
		mux {
		pins = "gpio65";
		function = "gpio";
		};

		config {
		pins = "gpio65";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		/* pcie_ep_wake_groups */
		pcie_ep0_wake_default: pcie_ep0_wake_default {
		mux {
		pins = "gpio61";
		function = "gpio";
		};

		config {
		pins = "gpio61";
		drive-strength = <2>;
		bias-disable; /* NO pull */
		};
		};
		};

		/* QDSD pin type; num-pins(6):clk,cmd,data0,data1,data2,data3 */

		/* PIN group 0 : qdsd_clk */

+3 −3

Original line number	Diff line number	Diff line
		@@ -301,8 +301,8 @@
		"int_link_down", "int_bridge_flush_n";

		pinctrl-names = "default";
		pinctrl-0 = <&pcie0_clkreq_default
		&pcie0_perst_default &pcie0_wake_default>;
		pinctrl-0 = <&pcie_ep0_clkreq_default
		&pcie_ep0_perst_default &pcie_ep0_wake_default>;

		perst-gpio = <&tlmm_pinmux 65 0>;
		wake-gpio = <&tlmm_pinmux 61 0>;
		@@ -325,7 +325,7 @@
		"pcie_0_aux_clk", "pcie_0_ldo",
		"pcie_0_phy_reset";
		max-clock-frequency-hz = <125000000>, <0>,
		<0>, <0>, <1000000>, <0>, <0>;
		<0>, <0>, <1010000>, <0>, <0>;

		qcom,msm-bus,name = "pcie-ep";
		qcom,msm-bus,num-cases = <2>;