Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fa0ce403 authored by Will Deacon's avatar Will Deacon Committed by Russell King
Browse files

ARM: 7162/1: errata: tidy up Kconfig options for PL310 errata workarounds 



The Kconfig options for the PL310 errata workarounds do not use a
consistent naming scheme for either the config option or the bool
description.

This patch tidies up the options by ensuring that the bool descriptions
are prefixed with "PL310 errata:" and the config options are prefixed
with PL310_ERRATA_, making it much clearer in menuconfig as to what the
workarounds are for.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 11ed0ba1

arch/arm/Kconfig

+4 −4
Original line number Diff line number Diff line
@@ -1231,7 +1231,7 @@ config ARM_ERRATA_742231 
	  capabilities of the processor.



config PL310_ERRATA_588369

	bool "Clean & Invalidate maintenance operations do not invalidate clean lines"

	bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"

	depends on CACHE_L2X0

	help

	   The PL310 L2 cache controller implements three types of Clean &
@@ -1256,7 +1256,7 @@ config ARM_ERRATA_720789 
	  entries regardless of the ASID.



config PL310_ERRATA_727915

	bool "Background Clean & Invalidate by Way operation can cause data corruption"

	bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"

	depends on CACHE_L2X0

	help

	  PL310 implements the Clean & Invalidate by Way L2 cache maintenance
@@ -1289,8 +1289,8 @@ config ARM_ERRATA_751472 
	  operation is received by a CPU before the ICIALLUIS has completed,

	  potentially leading to corrupted entries in the cache or TLB.



config ARM_ERRATA_753970

	bool "ARM errata: cache sync operation may be faulty"

config PL310_ERRATA_753970

	bool "PL310 errata: cache sync operation may be faulty"

	depends on CACHE_PL310

	help

	  This option enables the workaround for the 753970 PL310 (r3p0) erratum.

arch/arm/mm/cache-l2x0.c

+1 −1
Original line number Diff line number Diff line
@@ -61,7 +61,7 @@ static inline void cache_sync(void) 
{

	void __iomem *base = l2x0_base;



#ifdef CONFIG_ARM_ERRATA_753970

#ifdef CONFIG_PL310_ERRATA_753970

	/* write to an unmmapped register */

	writel_relaxed(0, base + L2X0_DUMMY_REG);

#else