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Commit f9e5908f authored by Janusz Krzysztofik's avatar Janusz Krzysztofik Committed by Tony Lindgren
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ARM: OMAP1: Update dpll1 default rate reprogramming method 



According to comments in omap1_select_table_rate(), reprogramming dpll1
is tricky, and should always be done from SRAM.

While being at it, move OMAP730 special case handling inside
omap_sram_reprogram_clock().

Created on top of version 2 of the series "ARM: OMAP1: Fix dpll1
reprogramming related issues", which it depends on.
Tested on Amstrad Delta.

Signed-off-by: default avatarJanusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 24ce2705

arch/arm/mach-omap1/clock.c

+1 −5
Original line number Diff line number Diff line
@@ -218,11 +218,7 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) 
	/*

	 * In most cases we should not need to reprogram DPLL.

	 * Reprogramming the DPLL is tricky, it must be done from SRAM.

	 * (on 730, bit 13 must always be 1)

	 */

	if (cpu_is_omap7xx())

		omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);

	else

	omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);



	/* XXX Do we need to recalculate the tree below DPLL1 at this point? */

arch/arm/mach-omap1/clock_data.c

+5 −2
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#include <plat/clock.h>

#include <plat/cpu.h>

#include <plat/clkdev_omap.h>

#include <plat/sram.h>	/* for omap_sram_reprogram_clock() */

#include <plat/usb.h>   /* for OTG_BASE */



#include "clock.h"
@@ -944,8 +945,10 @@ void __init omap1_clk_late_init(void) 
	/* Find the highest supported frequency and enable it */

	if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {

		pr_err("System frequencies not set, using default. Check your config.\n");

		omap_writew(0x2290, DPLL_CTL);

		omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL);

		/*

		 * Reprogramming the DPLL is tricky, it must be done from SRAM.

		 */

		omap_sram_reprogram_clock(0x2290, 0x0005);

		ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;

	}

	propagate_rate(&ck_dpll1);

arch/arm/plat-omap/sram.c

+3 −0
Original line number Diff line number Diff line
@@ -222,6 +222,9 @@ static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); 
void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)

{

	BUG_ON(!_omap_sram_reprogram_clock);

	/* On 730, bit 13 must always be 1 */

	if (cpu_is_omap7xx())

		ckctl |= 0x2000;

	_omap_sram_reprogram_clock(dpllctl, ckctl);

}