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Commit f9e011b6 authored by Ben Dooks's avatar Ben Dooks
Browse files

ARM: SAMSUNG: Fix bug in clksrc-clk round_rate call. 



The call has been assuming all clksrc-clks' divider size is 4 bits, but
this may not be the case anymore. Use the reg_div.size parameter to
calculate the maximum value it can take and check against that.

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
parent f3b464cc

arch/arm/plat-samsung/clock-clksrc.c

+5 −3
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate) 


	rate = clk_round_rate(clk, rate);

	div = clk_get_rate(clk->parent) / rate;

	if (div > 16)

	if (div > (1 << sclk->reg_div.size))

		return -EINVAL;



	val = __raw_readl(reg);
@@ -102,7 +102,9 @@ static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent) 
static unsigned long s3c_roundrate_clksrc(struct clk *clk,

					      unsigned long rate)

{

	struct clksrc_clk *sclk = to_clksrc(clk);

	unsigned long parent_rate = clk_get_rate(clk->parent);

	int max_div = 1 << sclk->reg_div.size;

	int div;



	if (rate >= parent_rate)
@@ -114,8 +116,8 @@ static unsigned long s3c_roundrate_clksrc(struct clk *clk, 


		if (div == 0)

			div = 1;

		if (div > 16)

			div = 16;

		if (div > max_div)

			div = max_div;



		rate = parent_rate / div;

	}