Loading drivers/video/msm/mdss/mdss_dsi.h +2 −1 Original line number Diff line number Diff line Loading @@ -56,9 +56,10 @@ #define MDSS_DSI_HW_REV_101_1 0x10010001 /* 8974Pro */ #define MDSS_DSI_HW_REV_102 0x10020000 /* 8084 */ #define MDSS_DSI_HW_REV_103 0x10030000 /* 8994 */ #define MDSS_DSI_HW_REV_103_1 0x10030001 /* 8916/8936/8937 */ #define MDSS_DSI_HW_REV_103_1 0x10030001 /* 8916/8936 */ #define MDSS_DSI_HW_REV_104 0x10040000 /* 8996 */ #define MDSS_DSI_HW_REV_104_1 0x10040001 /* 8996 */ #define MDSS_DSI_HW_REV_104_2 0x10040002 /* 8937 */ #define NONE_PANEL "none" Loading drivers/video/msm/mdss/msm_mdss_io_8974.c +5 −2 Original line number Diff line number Diff line Loading @@ -199,7 +199,10 @@ static void mdss_dsi_28nm_phy_regulator_enable( MIPI_OUTP((ctrl_pdata->phy_regulator_io.base) + 0x10, pd->regulator[4]); /* LDO ctrl */ if (MIPI_INP(ctrl_pdata->ctrl_base) == MDSS_DSI_HW_REV_103_1) if ((ctrl_pdata->shared_data->hw_rev == MDSS_DSI_HW_REV_103_1) || (ctrl_pdata->shared_data->hw_rev == MDSS_DSI_HW_REV_104_2)) MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x1dc, 0x05); else MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x1dc, 0x0d); Loading Loading @@ -245,7 +248,7 @@ static void mdss_dsi_28nm_phy_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata) pd = &(((ctrl_pdata->panel_data).panel_info.mipi).dsi_phy_db); /* Strength ctrl 0 for 28nm PHY*/ if ((ctrl_pdata->shared_data->hw_rev <= MDSS_DSI_HW_REV_103_1) && if ((ctrl_pdata->shared_data->hw_rev <= MDSS_DSI_HW_REV_104_2) && (ctrl_pdata->shared_data->hw_rev != MDSS_DSI_HW_REV_103)) { MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0170, 0x5b); MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0184, pd->strength[0]); Loading Loading
drivers/video/msm/mdss/mdss_dsi.h +2 −1 Original line number Diff line number Diff line Loading @@ -56,9 +56,10 @@ #define MDSS_DSI_HW_REV_101_1 0x10010001 /* 8974Pro */ #define MDSS_DSI_HW_REV_102 0x10020000 /* 8084 */ #define MDSS_DSI_HW_REV_103 0x10030000 /* 8994 */ #define MDSS_DSI_HW_REV_103_1 0x10030001 /* 8916/8936/8937 */ #define MDSS_DSI_HW_REV_103_1 0x10030001 /* 8916/8936 */ #define MDSS_DSI_HW_REV_104 0x10040000 /* 8996 */ #define MDSS_DSI_HW_REV_104_1 0x10040001 /* 8996 */ #define MDSS_DSI_HW_REV_104_2 0x10040002 /* 8937 */ #define NONE_PANEL "none" Loading
drivers/video/msm/mdss/msm_mdss_io_8974.c +5 −2 Original line number Diff line number Diff line Loading @@ -199,7 +199,10 @@ static void mdss_dsi_28nm_phy_regulator_enable( MIPI_OUTP((ctrl_pdata->phy_regulator_io.base) + 0x10, pd->regulator[4]); /* LDO ctrl */ if (MIPI_INP(ctrl_pdata->ctrl_base) == MDSS_DSI_HW_REV_103_1) if ((ctrl_pdata->shared_data->hw_rev == MDSS_DSI_HW_REV_103_1) || (ctrl_pdata->shared_data->hw_rev == MDSS_DSI_HW_REV_104_2)) MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x1dc, 0x05); else MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x1dc, 0x0d); Loading Loading @@ -245,7 +248,7 @@ static void mdss_dsi_28nm_phy_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata) pd = &(((ctrl_pdata->panel_data).panel_info.mipi).dsi_phy_db); /* Strength ctrl 0 for 28nm PHY*/ if ((ctrl_pdata->shared_data->hw_rev <= MDSS_DSI_HW_REV_103_1) && if ((ctrl_pdata->shared_data->hw_rev <= MDSS_DSI_HW_REV_104_2) && (ctrl_pdata->shared_data->hw_rev != MDSS_DSI_HW_REV_103)) { MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0170, 0x5b); MIPI_OUTP((ctrl_pdata->phy_io.base) + 0x0184, pd->strength[0]); Loading