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Commit f960442f authored by Vikram Mulukutla's avatar Vikram Mulukutla Committed by Matt Wagantall
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clk: qcom: clock-cpu-8996: Add measurement capability 



The CPU clocks on MSM8996 can be measured via
the GCC debug mux. Add support for this feature.

Change-Id: I1c2b51ee862b35fa547595b7d7436469532ecc6e
Signed-off-by: default avatarVikram Mulukutla <markivx@codeaurora.org>
parent f0ba8b55

arch/arm/boot/dts/qcom/msm8996.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -721,8 +721,9 @@ 
		      <0x06400000 0x1000>,

		      <0x06480000 0x1000>,

		      <0x09A11000 0x1000>,

		      <0x00070130    0x8>;

		reg-names = "pwrcl_pll", "perfcl_pll", "cbf_pll", "pwrcl_mux", "perfcl_mux", "cbf_mux", "efuse";

		      <0x00070130    0x8>,

		      <0x09820000 0x1000>;

		reg-names = "pwrcl_pll", "perfcl_pll", "cbf_pll", "pwrcl_mux", "perfcl_mux", "cbf_mux", "efuse", "debug";

		vdd-pwrcl-supply = <&apc0_vreg>;

		vdd-perfcl-supply = <&apc1_vreg>;

		vdd-cbf-supply = <&apc0_vreg>;
@@ -836,9 +837,10 @@ 
		compatible = "qcom,cc-debug-8996";

		reg = <0x362000 0x4>;

		reg-names = "cc_base";

		clock-names = "debug_mmss_clk", "debug_gpu_clk";

		clock-names = "debug_mmss_clk", "debug_gpu_clk", "debug_cpu_clk";

		clocks = <&clock_mmss clk_mmss_gcc_dbg_clk>,

			 <&clock_gpu clk_gpu_gcc_dbg_clk>;

			 <&clock_gpu clk_gpu_gcc_dbg_clk>,

			 <&clock_cpu clk_cpu_debug_mux>;

		#clock-cells = <1>;

	};

drivers/clk/msm/clock-cpu-8996.c

+86 −73
Original line number Diff line number Diff line
@@ -45,6 +45,7 @@ enum { 
	APC1_BASE,

	CBF_BASE,

	EFUSE_BASE,

	DEBUG_BASE,

	NUM_BASES

};
@@ -56,6 +57,7 @@ static char *base_names[] = { 
	"perfcl_mux",

	"cbf_mux",

	"efuse",

	"debug",

};



static void *vbases[NUM_BASES];
@@ -102,7 +104,7 @@ static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL); 
#define CBF_PLL_STATUS      0x28

#define CBF_PLL_TEST_CTL_LO 0x30



#define GLB_CLK_DIAG	0x1C

#define APC_DIAG_OFFSET	0x48

#define MUX_OFFSET	0x40



DEFINE_EXT_CLK(xo_ao, NULL);
@@ -247,6 +249,53 @@ static void cpu_mux_disable(struct mux_clk *mux) 
	__cpu_mux_set_sel(mux, mux->safe_sel);

}



/* It is assumed that the mux enable state is locked in this function */

static int cpu_debug_mux_set_sel(struct mux_clk *mux, int sel)

{

	__cpu_mux_set_sel(mux, sel);



	return 0;

}



static int cpu_debug_mux_get_sel(struct mux_clk *mux)

{

	u32 regval = readl_relaxed(*mux->base + mux->offset);

	return (regval >> mux->shift) & mux->mask;

}



static int cpu_debug_mux_enable(struct mux_clk *mux)

{

	u32 val;



	/* Enable debug clocks */

	val = readl_relaxed(vbases[APC0_BASE] + APC_DIAG_OFFSET);

	val |= BM(11, 8);

	writel_relaxed(val, vbases[APC0_BASE] + APC_DIAG_OFFSET);



	val = readl_relaxed(vbases[APC1_BASE] + APC_DIAG_OFFSET);

	val |= BM(11, 8);

	writel_relaxed(val, vbases[APC1_BASE] + APC_DIAG_OFFSET);



	/* Ensure enable request goes through for correct measurement*/

	mb();

	udelay(5);

	return 0;

}



static void cpu_debug_mux_disable(struct mux_clk *mux)

{

	u32 val;



	/* Disable debug clocks */

	val = readl_relaxed(vbases[APC0_BASE] + APC_DIAG_OFFSET);

	val &= ~BM(11, 8);

	writel_relaxed(val, vbases[APC0_BASE] + APC_DIAG_OFFSET);



	val = readl_relaxed(vbases[APC1_BASE] + APC_DIAG_OFFSET);

	val &= ~BM(11, 8);

	writel_relaxed(val, vbases[APC1_BASE] + APC_DIAG_OFFSET);

}



static struct clk_mux_ops cpu_mux_ops = {

	.enable = cpu_mux_enable,

	.disable = cpu_mux_disable,
@@ -254,6 +303,13 @@ static struct clk_mux_ops cpu_mux_ops = { 
	.get_mux_sel = cpu_mux_get_sel,

};



static struct clk_mux_ops cpu_debug_mux_ops = {

	.enable = cpu_debug_mux_enable,

	.disable = cpu_debug_mux_disable,

	.set_mux_sel = cpu_debug_mux_set_sel,

	.get_mux_sel = cpu_debug_mux_get_sel,

};



static struct mux_clk pwrcl_lf_mux = {

	.offset = MUX_OFFSET,

	MUX_SRC_LIST(
@@ -394,76 +450,6 @@ static struct cpu_clk_8996 perfcl_clk = { 
	},

};



DEFINE_FIXED_SLAVE_DIV_CLK(pwrcl_div_clk, 1, &pwrcl_clk.c);

DEFINE_FIXED_SLAVE_DIV_CLK(perfcl_div_clk, 1, &perfcl_clk.c);



#define APCS_ALIAS1_CORE_CBCR 0x58



static struct mux_clk pwrcl_debug_mux = {

	.offset = GLB_CLK_DIAG,

	.en_offset = APCS_ALIAS1_CORE_CBCR,

	.en_mask = 0x1,

	.ops = &mux_reg_ops,

	.mask = 0x3F,

	.shift = 12,

	MUX_REC_SRC_LIST(

		&pwrcl_div_clk.c,

	),

	MUX_SRC_LIST(

		{&pwrcl_div_clk.c, 0},

	),

	.base = &vbases[APC0_BASE],

	.c = {

		.dbg_name = "pwrcl_debug_mux",

		.ops = &clk_ops_gen_mux,

		CLK_INIT(pwrcl_debug_mux.c),

	},

};



#define APCS_ALIAS0_CORE_CBCR 0x58



static struct mux_clk perfcl_debug_mux = {

	.offset = GLB_CLK_DIAG,

	.en_offset = APCS_ALIAS0_CORE_CBCR,

	.en_mask = 0x1,

	.ops = &mux_reg_ops,

	.mask = 0x3F,

	.shift = 12,

	MUX_REC_SRC_LIST(

		&perfcl_div_clk.c,

	),

	MUX_SRC_LIST(

		{&perfcl_div_clk.c, 0},

	),

	.base = &vbases[APC1_BASE],

	.c = {

		.dbg_name = "perfcl_debug_mux",

		.ops = &clk_ops_gen_mux,

		CLK_INIT(perfcl_debug_mux.c),

	},

};



static struct mux_clk cpu_debug_mux = {

	.offset = 0x120,

	.ops = &cpu_mux_ops,

	.mask = 0x1,

	.shift = 0,

	MUX_SRC_LIST(

		{&pwrcl_debug_mux.c, 0},

		{&perfcl_debug_mux.c, 1},

	),

	MUX_REC_SRC_LIST(

		&pwrcl_debug_mux.c,

		&perfcl_debug_mux.c,

	),

	.base = &vbases[CBF_BASE],

	.c = {

		.dbg_name = "cpu_debug_mux",

		.ops = &clk_ops_gen_mux,

		CLK_INIT(cpu_debug_mux.c),

	},

};



static struct clk *logical_cpu_to_clk(int cpu)

{

	struct device_node *cpu_node;
@@ -573,6 +559,35 @@ static struct mux_clk cbf_hf_mux = { 
	},

};



#define APCS_CLK_DIAG 0x78



DEFINE_FIXED_SLAVE_DIV_CLK(pwrcl_div_clk, 16, &pwrcl_clk.c);

DEFINE_FIXED_SLAVE_DIV_CLK(perfcl_div_clk, 16, &perfcl_clk.c);



static struct mux_clk cpu_debug_mux = {

	.offset = APCS_CLK_DIAG,

	MUX_SRC_LIST(

		{ &cbf_hf_mux.c, 0x01 },

		{ &pwrcl_div_clk.c,  0x11 },

		{ &perfcl_div_clk.c, 0x21 },

	),

	MUX_REC_SRC_LIST(

		&cbf_hf_mux.c,

		&pwrcl_div_clk.c,

		&perfcl_div_clk.c,

	),

	.ops = &cpu_debug_mux_ops,

	.mask = 0xFF,

	.shift = 8,

	.base = &vbases[DEBUG_BASE],

	.c = {

		.dbg_name = "cpu_debug_mux",

		.ops = &clk_ops_gen_mux,

		.flags = CLKFLAG_NO_RATE_CACHE,

		CLK_INIT(cpu_debug_mux.c),

	},

};



static struct clk_lookup cpu_clocks_8996[] = {

	CLK_LIST(pwrcl_clk),

	CLK_LIST(pwrcl_pll),
@@ -593,8 +608,6 @@ static struct clk_lookup cpu_clocks_8996[] = { 
	CLK_LIST(xo_ao),

	CLK_LIST(sys_apcsaux_clk),



	CLK_LIST(pwrcl_debug_mux),

	CLK_LIST(perfcl_debug_mux),

	CLK_LIST(cpu_debug_mux),

};

drivers/clk/msm/clock-gcc-8996.c

+7 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL); 


DEFINE_EXT_CLK(mmss_gcc_dbg_clk, NULL);

DEFINE_EXT_CLK(gpu_gcc_dbg_clk, NULL);

DEFINE_EXT_CLK(cpu_dbg_clk, NULL);

DEFINE_CLK_RPM_SMD_BRANCH(cxo_clk_src, cxo_clk_src_ao, RPM_MISC_CLK_TYPE,

				CXO_CLK_SRC_ID, 19200000);

DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_CLK_ID, NULL);
@@ -3168,11 +3169,13 @@ static struct mux_clk gcc_debug_mux = { 
		&mmss_gcc_dbg_clk.c,

		&gpu_gcc_dbg_clk.c,

		&gcc_debug_mux_v2.c,

		&cpu_dbg_clk.c,

	),

	MUX_SRC_LIST(

		{ &mmss_gcc_dbg_clk.c, 0x001b },

		{ &gpu_gcc_dbg_clk.c, 0x001b },

		{ &gcc_debug_mux_v2.c, 0xffff },

		{ &cpu_dbg_clk.c, 0x00bb },

		{ &cnoc_clk.c, 0x000e },

		{ &pnoc_clk.c, 0x0011 },

		{ &snoc_clk.c, 0x0000 },
@@ -3731,6 +3734,7 @@ arch_initcall(msm_gcc_8996_init); 
static struct clk_lookup msm_clocks_measure_8996[] = {

	CLK_LIST(mmss_gcc_dbg_clk),

	CLK_LIST(gpu_gcc_dbg_clk),

	CLK_LIST(cpu_dbg_clk),

	CLK_LOOKUP_OF("measure", gcc_debug_mux, "debug"),

};
@@ -3738,6 +3742,7 @@ static struct clk_lookup msm_clocks_measure_8996_v2[] = { 
	CLK_LIST(mmss_gcc_dbg_clk),

	CLK_LIST(gpu_gcc_dbg_clk),

	CLK_LIST(gcc_debug_mux_v2),

	CLK_LIST(cpu_dbg_clk),

	CLK_LOOKUP_OF("measure", gcc_debug_mux, "debug"),

};
@@ -3770,6 +3775,8 @@ static int msm_clock_debug_8996_probe(struct platform_device *pdev) 


	mmss_gcc_dbg_clk.dev = &pdev->dev;

	mmss_gcc_dbg_clk.clk_id = "debug_mmss_clk";

	cpu_dbg_clk.dev = &pdev->dev;

	cpu_dbg_clk.clk_id = "debug_cpu_clk";



	gpu_gcc_dbg_clk.dev = &pdev->dev;

	gpu_gcc_dbg_clk.clk_id = "debug_gpu_clk";

include/dt-bindings/clock/msm-clocks-8996.h

+1 −2
Original line number Diff line number Diff line
@@ -147,6 +147,7 @@ 
#define clk_gcc_qusb2phy_sec_reset	0x3f3a87d0

#define clk_gcc_periph_noc_usb20_ahb_clk	0xfb9f26e9

#define clk_gcc_mmss_gcc_dbg_clk	0xe89d461c

#define clk_cpu_dbg_clk			0x6550dfa9

#define clk_gcc_blsp1_ahb_clk		0x8caa5b4f

#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9

#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0
@@ -517,8 +518,6 @@ 
#define clk_cbf_lf_mux 0x8abdf099

#define clk_xo_ao 0x428c856d

#define clk_sys_apcsaux_clk 0x0b0dd513

#define clk_pwrcl_debug_mux 0xf4405808

#define clk_perfcl_debug_mux 0xf107e489

#define clk_cpu_debug_mux 0xc7acaa31



/* Audio External Clocks */