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Commit f90b84dd authored by Gopikrishnaiah Anandan's avatar Gopikrishnaiah Anandan Committed by Gerrit - the friendly Code Review server
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mdss: mdp: update 3d gamut programming sequence 



3D Gamut block programming sequence requires disabling the clock gating
when the tables of the feature are being programmed. Clock gating can be
enabled on the next vsync after the gamut settings have been flushed.
Change implements the recommended programming sequence to resolve image
screen corruption issues.

Change-Id: If99007debb00b358c9d6266dcc2240269b9947aa
Signed-off-by: default avatarGopikrishnaiah Anandan <agopik@codeaurora.org>
parent c2e38a43

drivers/video/msm/mdss/mdss_mdp_pp.c

+3 −1
Original line number Diff line number Diff line
@@ -1749,7 +1749,9 @@ static int pp_dspp_setup(u32 disp_num, struct mdss_mdp_mixer *mixer) 
	}



	mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON);



	if (pp_driver_ops.gamut_clk_gate_en)

		pp_driver_ops.gamut_clk_gate_en(base +

					mdata->pp_block_off.dspp_gamut_off);

	ret = pp_hist_setup(&opmode, MDSS_PP_DSPP_CFG | dspp_num, mixer);

	if (ret)

		goto dspp_exit;

drivers/video/msm/mdss/mdss_mdp_pp.h

+1 −0
Original line number Diff line number Diff line
@@ -98,6 +98,7 @@ struct mdp_pp_driver_ops { 
	int (*get_hist_offset)(u32 block, u32 *ctl_off);

	int (*get_hist_isr_info)(u32 *isr_mask);

	bool (*is_sspp_hist_supp)(void);

	void (*gamut_clk_gate_en)(char __iomem *base_addr);

};



struct mdss_pp_res_type_v1_7 {

drivers/video/msm/mdss/mdss_mdp_pp_v1_7.c

+26 −1
Original line number Diff line number Diff line
@@ -51,6 +51,9 @@ 
#define GAMUT_FINE_INDEX 0

#define GAMUT_MAP_EN BIT(1)

#define GAMUT_ENABLE BIT(0)

#define GAMUT_CLK_GATING_ACTIVE 0x0

#define GAMUT_CLK_GATING_PARTIAL_ACTIVE 0x11

#define GAMUT_CLK_GATING_INACTIVE 0x33



#define IGC_MASK_MAX 3

#define IGC_C0_LUT 0
@@ -237,6 +240,7 @@ static int pp_pa_get_version(u32 *version); 
static int pp_gamut_get_version(u32 *version);

static int pp_dither_get_version(u32 *version);

static int pp_hist_lut_get_version(u32 *version);

static void pp_gamut_clock_gating_en(char __iomem *base_addr);



void *pp_get_driver_ops(struct mdp_pp_driver_ops *ops)

{
@@ -295,7 +299,7 @@ void *pp_get_driver_ops(struct mdp_pp_driver_ops *ops) 
	ops->get_hist_offset = pp_get_hist_offset;

	ops->get_hist_isr_info = pp_get_hist_isr;

	ops->is_sspp_hist_supp = pp_is_sspp_hist_supp;



	ops->gamut_clk_gate_en = pp_gamut_clock_gating_en;

	return &config_data;

}
@@ -681,6 +685,7 @@ static int pp_gamut_get_config(char __iomem *base_addr, void *cfg_data, 
	struct mdp_gamut_cfg_data *gamut_cfg = (struct mdp_gamut_cfg_data *)

						cfg_data;

	struct mdp_gamut_data_v1_7 gamut_data;

	u32 clk_gate_disable = 0;



	if (!base_addr || !cfg_data) {

		pr_err("invalid params base_addr %p cfg_data %p\n",
@@ -742,6 +747,8 @@ static int pp_gamut_get_config(char __iomem *base_addr, void *cfg_data, 
	}

	gamut_c0 = gamut_tbl;

	gamut_c1c2 = gamut_c0 + tbl_sz;

	writel_relaxed(GAMUT_CLK_GATING_INACTIVE, base_addr + GAMUT_CLK_CTRL);

	clk_gate_disable = 1;

	for (i = 0; i < MDP_GAMUT_TABLE_NUM_V1_7; i++) {

		val = index_start;

		val |= GAMUT_READ_TABLE_EN;
@@ -802,6 +809,9 @@ static int pp_gamut_get_config(char __iomem *base_addr, void *cfg_data, 
		ret = -EFAULT;

	}

bail_out:

	if (clk_gate_disable)

		writel_relaxed(GAMUT_CLK_GATING_PARTIAL_ACTIVE,

					   base_addr + GAMUT_CLK_CTRL);

	kfree(gamut_tbl);

	return ret;

}
@@ -877,6 +887,7 @@ static int pp_gamut_set_config(char __iomem *base_addr, 
		}

	}

	base_addr_scale += GAMUT_C0_SCALE_OFF;

	writel_relaxed(GAMUT_CLK_GATING_INACTIVE, base_addr + GAMUT_CLK_CTRL);

	for (i = 0; i < MDP_GAMUT_TABLE_NUM_V1_7; i++) {

		val = index_start;

		val |= GAMUT_TABLE_SELECT(i);
@@ -895,6 +906,8 @@ static int pp_gamut_set_config(char __iomem *base_addr, 
			base_addr_scale += 4;

		}

	}

	writel_relaxed(GAMUT_CLK_GATING_PARTIAL_ACTIVE,

				   base_addr + GAMUT_CLK_CTRL);

bail_out:

	if (!ret) {

		val = 0;
@@ -2128,3 +2141,15 @@ static int pp_hist_lut_get_version(u32 *version) 
	*version = mdp_hist_lut_v1_7;

	return 0;

}



static void pp_gamut_clock_gating_en(char __iomem *base_addr)

{

	u32 val;



	if (base_addr) {

		val = readl_relaxed(base_addr + GAMUT_CLK_CTRL);

		if (val == GAMUT_CLK_GATING_PARTIAL_ACTIVE)

			writel_relaxed(GAMUT_CLK_GATING_ACTIVE,

						   base_addr + GAMUT_CLK_CTRL);

	}

}