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Commit f9052cd4 authored by Amir Levy's avatar Amir Levy Committed by Gerrit - the friendly Code Review server
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msm: ipa3: new SRAM partitioning for IPAv3 



IPAv3 requires some changes in the SRAM partitioning:
- Routing tables - need 4 tables:
  IPv4 & IPv6 hashable tables - 120B each, 8B aligned
  IPv4 & IPv6 non-hashable tables - 120B each, 8B aligned
- Filtering tables - need 4 tables:
  IPv4 & IPv6 hashable tables - 120B each, 8B aligned
  IPv4 & IPv6 non-hashable tables - 120B each, 8B aligned
- Modem memory partition is reduced to 5160B, to account for
  the new routing/filtering requirements.

Change-Id: I1254afbc293eeba98f029355240db27e93cd9693
Signed-off-by: default avatarSivan Reinstein <sivanr@codeaurora.org>
Signed-off-by: default avatarGhanim Fodi <gfodi@codeaurora.org>
Signed-off-by: default avatarAmir Levy <alevy@codeaurora.org>
parent 9dc5ffb8

drivers/platform/msm/ipa/ipa_v3/ipa.c

+16 −0
Original line number Diff line number Diff line
@@ -1688,13 +1688,29 @@ int _ipa_init_sram_v3_0(void) 
	}



	/* Consult with ipa_ram_mmap.h on the location of the CANARY values */

	ipa3_sram_set_canary(ipa_sram_mmio,

		IPA_MEM_PART(v4_flt_hashable_ofst) - 4);

	ipa3_sram_set_canary(ipa_sram_mmio,

		IPA_MEM_PART(v4_flt_hashable_ofst));

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v4_flt_ofst) - 4);

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v4_flt_ofst));

	ipa3_sram_set_canary(ipa_sram_mmio,

		IPA_MEM_PART(v6_flt_hashable_ofst) - 4);

	ipa3_sram_set_canary(ipa_sram_mmio,

		IPA_MEM_PART(v6_flt_hashable_ofst));

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v6_flt_ofst) - 4);

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v6_flt_ofst));

	ipa3_sram_set_canary(ipa_sram_mmio,

		IPA_MEM_PART(v4_rt_hashable_ofst) - 4);

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v4_rt_hashable_ofst));

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v4_rt_ofst) - 4);

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v4_rt_ofst));

	ipa3_sram_set_canary(ipa_sram_mmio,

		IPA_MEM_PART(v6_rt_hashable_ofst) - 4);

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v6_rt_hashable_ofst));

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v6_rt_ofst) - 4);

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(v6_rt_ofst));

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(modem_hdr_ofst) - 4);

	ipa3_sram_set_canary(ipa_sram_mmio, IPA_MEM_PART(modem_hdr_ofst));

	ipa3_sram_set_canary(ipa_sram_mmio,

		IPA_MEM_PART(modem_hdr_proc_ctx_ofst) - 4);

drivers/platform/msm/ipa/ipa_v3/ipa_i.h

+22 −0
Original line number Diff line number Diff line
@@ -1284,12 +1284,26 @@ struct ipa3_mem_partition { 
	u16 ofst_start;

	u16 nat_ofst;

	u16 nat_size;

	u16 v4_flt_hashable_ofst;

	u16 v4_flt_hashable_size;

	u16 v4_flt_hashable_size_ddr;

	u16 v4_flt_ofst;

	u16 v4_flt_size;

	u16 v4_flt_size_ddr;

	u16 v6_flt_hashable_ofst;

	u16 v6_flt_hashable_size;

	u16 v6_flt_hashable_size_ddr;

	u16 v6_flt_ofst;

	u16 v6_flt_size;

	u16 v6_flt_size_ddr;

	u16 v4_rt_hashable_ofst;

	u16 v4_hashable_num_index;

	u16 v4_modem_rt_hashable_index_lo;

	u16 v4_modem_rt_hashable_index_hi;

	u16 v4_apps_rt_hashable_index_lo;

	u16 v4_apps_rt_hashable_index_hi;

	u16 v4_rt_hashable_size;

	u16 v4_rt_hashable_size_ddr;

	u16 v4_rt_ofst;

	u16 v4_num_index;

	u16 v4_modem_rt_index_lo;
@@ -1298,6 +1312,14 @@ struct ipa3_mem_partition { 
	u16 v4_apps_rt_index_hi;

	u16 v4_rt_size;

	u16 v4_rt_size_ddr;

	u16 v6_rt_hashable_ofst;

	u16 v6_hashable_num_index;

	u16 v6_modem_rt_hashable_index_lo;

	u16 v6_modem_rt_hashable_index_hi;

	u16 v6_apps_rt_hashable_index_lo;

	u16 v6_apps_rt_hashable_index_hi;

	u16 v6_rt_hashable_size;

	u16 v6_rt_hashable_size_ddr;

	u16 v6_rt_ofst;

	u16 v6_num_index;

	u16 v6_modem_rt_index_lo;

drivers/platform/msm/ipa/ipa_v3/ipa_ram_mmap.h

+150 −230
Original line number Diff line number Diff line
@@ -23,23 +23,6 @@ 
#define IPA_RAM_NAT_OFST    0

#define IPA_RAM_NAT_SIZE    0



#define IPA_MEM_v1_RAM_HDR_OFST    (IPA_RAM_NAT_OFST + IPA_RAM_NAT_SIZE)

#define IPA_MEM_v1_RAM_HDR_SIZE    1664

#define IPA_MEM_v1_RAM_V4_FLT_OFST (IPA_MEM_v1_RAM_HDR_OFST +\

	IPA_MEM_v1_RAM_HDR_SIZE)

#define IPA_MEM_v1_RAM_V4_FLT_SIZE 2176

#define IPA_MEM_v1_RAM_V4_RT_OFST  (IPA_MEM_v1_RAM_V4_FLT_OFST +\

	IPA_MEM_v1_RAM_V4_FLT_SIZE)

#define IPA_MEM_v1_RAM_V4_RT_SIZE  512

#define IPA_MEM_v1_RAM_V6_FLT_OFST (IPA_MEM_v1_RAM_V4_RT_OFST +\

	IPA_MEM_v1_RAM_V4_RT_SIZE)

#define IPA_MEM_v1_RAM_V6_FLT_SIZE 1792

#define IPA_MEM_v1_RAM_V6_RT_OFST  (IPA_MEM_v1_RAM_V6_FLT_OFST +\

	IPA_MEM_v1_RAM_V6_FLT_SIZE)

#define IPA_MEM_v1_RAM_V6_RT_SIZE  512

#define IPA_MEM_v1_RAM_END_OFST    (IPA_MEM_v1_RAM_V6_RT_OFST +\

	IPA_MEM_v1_RAM_V6_RT_SIZE)



#define IPA_MEM_RAM_V6_RT_SIZE_DDR 16384

#define IPA_MEM_RAM_V4_RT_SIZE_DDR 16384

#define IPA_MEM_RAM_V6_FLT_SIZE_DDR 16384
@@ -50,203 +33,81 @@ 
#define IPA_MEM_CANARY_VAL 0xdeadbeef



#define IPA_MEM_RAM_MODEM_NETWORK_STATS_SIZE 256





/*

 * IPA v2.0 and v2.1 SRAM memory layout:

 * +-------------+

 * | V4 FLT HDR  |

 * +-------------+

 * IPA v3.0 SRAM memory layout:

 * +-------------------------+

 * |    UC INFO              |

 * +-------------------------+

 * |    CANARY               |

 * +-------------+

 * +-------------------------+

 * |    CANARY               |

 * +-------------+

 * | V6 FLT HDR  |

 * +-------------+

 * +-------------------------+

 * | V4 FLT HDR HASHABLE     |

 * +-------------------------+

 * |    CANARY               |

 * +-------------+

 * +-------------------------+

 * |    CANARY               |

 * +-------------+

 * | V4 RT HDR   |

 * +-------------+

 * +-------------------------+

 * | V4 FLT HDR NON-HASHABLE |

 * +-------------------------+

 * |    CANARY               |

 * +-------------+

 * | V6 RT HDR   |

 * +-------------+

 * +-------------------------+

 * |    CANARY               |

 * +-------------+

 * |  MODEM HDR  |

 * +-------------+

 * |  APPS  HDR  |

 * +-------------+

 * +-------------------------+

 * | V6 FLT HDR HASHABLE     |

 * +-------------------------+

 * |    CANARY               |

 * +-------------+

 * |  MODEM MEM  |

 * +-------------+

 * +-------------------------+

 * |    CANARY               |

 * +-------------+

 * | APPS V4 FLT |

 * +-------------+

 * | APPS V6 FLT |

 * +-------------+

 * +-------------------------+

 * | V6 FLT HDR NON-HASHABLE |

 * +-------------------------+

 * |    CANARY               |

 * +-------------+

 * |   UC INFO   |

 * +-------------+

 */

#define IPA_MEM_v2_RAM_OFST_START 128

#define IPA_MEM_v2_RAM_V4_FLT_OFST IPA_MEM_v2_RAM_OFST_START

#define IPA_MEM_v2_RAM_V4_FLT_SIZE 88



/* V4 filtering header table is 8B aligned */

#if (IPA_MEM_v2_RAM_V4_FLT_OFST & 7)

#error V4 filtering header table is not 8B aligned

#endif



#define IPA_MEM_v2_RAM_V6_FLT_OFST (IPA_MEM_v2_RAM_V4_FLT_OFST + \

		IPA_MEM_v2_RAM_V4_FLT_SIZE + 2*IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v2_RAM_V6_FLT_SIZE 88



/* V6 filtering header table is 8B aligned */

#if (IPA_MEM_v2_RAM_V6_FLT_OFST & 7)

#error V6 filtering header table is not 8B aligned

#endif



#define IPA_MEM_v2_RAM_V4_RT_OFST (IPA_MEM_v2_RAM_V6_FLT_OFST + \

		IPA_MEM_v2_RAM_V6_FLT_SIZE + 2*IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v2_RAM_V4_NUM_INDEX 11

#define IPA_MEM_v2_V4_MODEM_RT_INDEX_LO 0

#define IPA_MEM_v2_V4_MODEM_RT_INDEX_HI 3

#define IPA_MEM_v2_V4_APPS_RT_INDEX_LO 4

#define IPA_MEM_v2_V4_APPS_RT_INDEX_HI 10

#define IPA_MEM_v2_RAM_V4_RT_SIZE (IPA_MEM_v2_RAM_V4_NUM_INDEX * 4)



/* V4 routing header table is 8B aligned */

#if (IPA_MEM_v2_RAM_V4_RT_OFST & 7)

#error V4 routing header table is not 8B aligned

#endif



#define IPA_MEM_v2_RAM_V6_RT_OFST (IPA_MEM_v2_RAM_V4_RT_OFST + \

		IPA_MEM_v2_RAM_V4_RT_SIZE + IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v2_RAM_V6_NUM_INDEX 11

#define IPA_MEM_v2_V6_MODEM_RT_INDEX_LO 0

#define IPA_MEM_v2_V6_MODEM_RT_INDEX_HI 3

#define IPA_MEM_v2_V6_APPS_RT_INDEX_LO 4

#define IPA_MEM_v2_V6_APPS_RT_INDEX_HI 10

#define IPA_MEM_v2_RAM_V6_RT_SIZE (IPA_MEM_v2_RAM_V6_NUM_INDEX * 4)



/* V6 routing header table is 8B aligned */

#if (IPA_MEM_v2_RAM_V6_RT_OFST & 7)

#error V6 routing header table is not 8B aligned

#endif



#define IPA_MEM_v2_RAM_MODEM_HDR_OFST (IPA_MEM_v2_RAM_V6_RT_OFST + \

		IPA_MEM_v2_RAM_V6_RT_SIZE + IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v2_RAM_MODEM_HDR_SIZE 320



/* header table is 8B aligned */

#if (IPA_MEM_v2_RAM_MODEM_HDR_OFST & 7)

#error header table is not 8B aligned

#endif



#define IPA_MEM_v2_RAM_APPS_HDR_OFST (IPA_MEM_v2_RAM_MODEM_HDR_OFST + \

		IPA_MEM_v2_RAM_MODEM_HDR_SIZE)

#define IPA_MEM_v2_RAM_APPS_HDR_SIZE 72



/* header table is 8B aligned */

#if (IPA_MEM_v2_RAM_APPS_HDR_OFST & 7)

#error header table is not 8B aligned

#endif



#define IPA_MEM_v2_RAM_MODEM_OFST (IPA_MEM_v2_RAM_APPS_HDR_OFST + \

		IPA_MEM_v2_RAM_APPS_HDR_SIZE + IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v2_RAM_MODEM_SIZE 3532



/* modem memory is 4B aligned */

#if (IPA_MEM_v2_RAM_MODEM_OFST & 3)

#error modem memory is not 4B aligned

#endif



#define IPA_MEM_v2_RAM_APPS_V4_FLT_OFST (IPA_MEM_v2_RAM_MODEM_OFST + \

		IPA_MEM_v2_RAM_MODEM_SIZE + IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v2_RAM_APPS_V4_FLT_SIZE 1920



/* filtering rule is 4B aligned */

#if (IPA_MEM_v2_RAM_APPS_V4_FLT_OFST & 3)

#error filtering rule is not 4B aligned

#endif



#define IPA_MEM_v2_RAM_APPS_V6_FLT_OFST (IPA_MEM_v2_RAM_APPS_V4_FLT_OFST + \

		IPA_MEM_v2_RAM_APPS_V4_FLT_SIZE)

#define IPA_MEM_v2_RAM_APPS_V6_FLT_SIZE 1372



/* filtering rule is 4B aligned */

#if (IPA_MEM_v2_RAM_APPS_V6_FLT_OFST & 3)

#error filtering rule is not 4B aligned

#endif



#define IPA_MEM_v2_RAM_UC_INFO_OFST (IPA_MEM_v2_RAM_APPS_V6_FLT_OFST + \

		IPA_MEM_v2_RAM_APPS_V6_FLT_SIZE + IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v2_RAM_UC_INFO_SIZE 292



/* uC info 4B aligned */

#if (IPA_MEM_v2_RAM_UC_INFO_OFST & 3)

#error uC info is not 4B aligned

#endif



#define IPA_MEM_v2_RAM_END_OFST (IPA_MEM_v2_RAM_UC_INFO_OFST + \

		IPA_MEM_v2_RAM_UC_INFO_SIZE)

#define IPA_MEM_v2_RAM_APPS_V4_RT_OFST IPA_MEM_v2_RAM_END_OFST

#define IPA_MEM_v2_RAM_APPS_V4_RT_SIZE 0

#define IPA_MEM_v2_RAM_APPS_V6_RT_OFST IPA_MEM_v2_RAM_END_OFST

#define IPA_MEM_v2_RAM_APPS_V6_RT_SIZE 0

#define IPA_MEM_v2_RAM_HDR_SIZE_DDR 4096



/*

 * IPA v3.0 SRAM memory layout:

 * +----------------+

 * |    UC INFO     |

 * +----------------+

 * +-------------------------+

 * |    CANARY               |

 * +-------------------------+

 * | V4 RT HDR HASHABLE      |

 * +-------------------------+

 * |    CANARY               |

 * +----------------+

 * +-------------------------+

 * |    CANARY               |

 * +----------------+

 * | V4 FLT HDR     |

 * +----------------+

 * +-------------------------+

 * | V4 RT HDR NON-HASHABLE  |

 * +-------------------------+

 * |    CANARY               |

 * +----------------+

 * +-------------------------+

 * |    CANARY               |

 * +----------------+

 * | V6 FLT HDR     |

 * +----------------+

 * +-------------------------+

 * | V6 RT HDR HASHABLE      |

 * +-------------------------+

 * |    CANARY               |

 * +----------------+

 * +-------------------------+

 * |    CANARY               |

 * +----------------+

 * | V4 RT HDR      |

 * +----------------+

 * +-------------------------+

 * | V6 RT HDR NON-HASHABLE  |

 * +-------------------------+

 * |    CANARY               |

 * +----------------+

 * | V6 RT HDR      |

 * +----------------+

 * +-------------------------+

 * |    CANARY               |

 * +----------------+

 * +-------------------------+

 * |  MODEM HDR              |

 * +----------------+

 * |  APPS  HDR     |

 * +----------------+

 * +-------------------------+

 * |    CANARY               |

 * +----------------+

 * +-------------------------+

 * |    CANARY               |

 * +----------------+

 * +-------------------------+

 * | MODEM PROC CTX          |

 * +----------------+

 * +-------------------------+

 * | APPS PROC CTX           |

 * +----------------+

 * +-------------------------+

 * |    CANARY               |

 * +----------------+

 * +-------------------------+

 * |  MODEM MEM              |

 * +----------------+

 * +-------------------------+

 * |    CANARY               |

 * +----------------+

 * +-------------------------+

 */



#define IPA_MEM_v3_0_RAM_UC_MEM_SIZE 128
@@ -261,26 +122,65 @@ 
#define IPA_MEM_v3_0_RAM_OFST_START (IPA_MEM_v3_0_RAM_UC_INFO_OFST + \

	IPA_MEM_v3_0_RAM_UC_INFO_SIZE)



#define IPA_MEM_v3_0_RAM_V4_FLT_OFST (IPA_MEM_v3_0_RAM_OFST_START + \

#define IPA_MEM_v3_0_RAM_V4_FLT_HASHABLE_OFST (IPA_MEM_v3_0_RAM_OFST_START + \

	2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V4_FLT_SIZE 88

#define IPA_MEM_v3_0_RAM_V4_FLT_HASHABLE_SIZE 120



/* V4 filtering header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V4_FLT_HASHABLE_OFST & 7)

#error V4 filtering hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_V4_FLT_OFST \

	(IPA_MEM_v3_0_RAM_V4_FLT_HASHABLE_OFST + \

	IPA_MEM_v3_0_RAM_V4_FLT_HASHABLE_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V4_FLT_SIZE 120



/* V4 filtering header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V4_FLT_OFST & 7)

#error V4 filtering header table is not 8B aligned

#error V4 filtering non-hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_V6_FLT_OFST (IPA_MEM_v3_0_RAM_V4_FLT_OFST + \

#define IPA_MEM_v3_0_RAM_V6_FLT_HASHABLE_OFST \

	(IPA_MEM_v3_0_RAM_V4_FLT_OFST + \

	IPA_MEM_v3_0_RAM_V4_FLT_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V6_FLT_SIZE 88

#define IPA_MEM_v3_0_RAM_V6_FLT_HASHABLE_SIZE 120



/* V6 filtering header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V6_FLT_HASHABLE_OFST & 7)

#error V6 filtering hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_V6_FLT_OFST \

	(IPA_MEM_v3_0_RAM_V6_FLT_HASHABLE_OFST + \

	IPA_MEM_v3_0_RAM_V6_FLT_HASHABLE_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V6_FLT_SIZE 120



/* V6 filtering header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V6_FLT_OFST & 7)

#error V6 filtering header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_V4_RT_OFST (IPA_MEM_v3_0_RAM_V6_FLT_OFST + \

#define IPA_MEM_v3_0_RAM_V4_RT_HASHABLE_OFST (IPA_MEM_v3_0_RAM_V6_FLT_OFST + \

	IPA_MEM_v3_0_RAM_V6_FLT_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V4_HASHABLE_NUM_INDEX 15

#define IPA_MEM_v3_0_V4_MODEM_RT_HASHABLE_INDEX_LO 0

#define IPA_MEM_v3_0_V4_MODEM_RT_HASHABLE_INDEX_HI 6

#define IPA_MEM_v3_0_V4_APPS_RT_HASHABLE_INDEX_LO \

	(IPA_MEM_v3_0_V4_MODEM_RT_HASHABLE_INDEX_HI + 1)

#define IPA_MEM_v3_0_V4_APPS_RT_HASHABLE_INDEX_HI \

	(IPA_MEM_v3_0_RAM_V4_HASHABLE_NUM_INDEX - 1)

#define IPA_MEM_v3_0_RAM_V4_RT_HASHABLE_SIZE \

	(IPA_MEM_v3_0_RAM_V4_HASHABLE_NUM_INDEX * 8)



/* V4 routing header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V4_RT_HASHABLE_OFST & 7)

#error V4 routing hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_V4_RT_OFST \

	(IPA_MEM_v3_0_RAM_V4_RT_HASHABLE_OFST + \

	IPA_MEM_v3_0_RAM_V4_RT_HASHABLE_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V4_NUM_INDEX 15

#define IPA_MEM_v3_0_V4_MODEM_RT_INDEX_LO 0

#define IPA_MEM_v3_0_V4_MODEM_RT_INDEX_HI 6
@@ -288,15 +188,33 @@ 
	(IPA_MEM_v3_0_V4_MODEM_RT_INDEX_HI + 1)

#define IPA_MEM_v3_0_V4_APPS_RT_INDEX_HI \

	(IPA_MEM_v3_0_RAM_V4_NUM_INDEX - 1)

#define IPA_MEM_v3_0_RAM_V4_RT_SIZE (IPA_MEM_v3_0_RAM_V4_NUM_INDEX * 4)

#define IPA_MEM_v3_0_RAM_V4_RT_SIZE \

	(IPA_MEM_v3_0_RAM_V4_NUM_INDEX * 8)



/* V4 routing header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V4_RT_OFST & 7)

#error V4 routing header table is not 8B aligned

#error V4 routing non-hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_V6_RT_HASHABLE_OFST (IPA_MEM_v3_0_RAM_V4_RT_OFST + \

	IPA_MEM_v3_0_RAM_V4_RT_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V6_HASHABLE_NUM_INDEX 15

#define IPA_MEM_v3_0_V6_MODEM_RT_HASHABLE_INDEX_LO 0

#define IPA_MEM_v3_0_V6_MODEM_RT_HASHABLE_INDEX_HI 6

#define IPA_MEM_v3_0_V6_APPS_RT_HASHABLE_INDEX_LO \

	(IPA_MEM_v3_0_V6_MODEM_RT_HASHABLE_INDEX_HI + 1)

#define IPA_MEM_v3_0_V6_APPS_RT_HASHABLE_INDEX_HI \

	(IPA_MEM_v3_0_RAM_V6_HASHABLE_NUM_INDEX - 1)

#define IPA_MEM_v3_0_RAM_V6_RT_HASHABLE_SIZE \

	(IPA_MEM_v3_0_RAM_V6_HASHABLE_NUM_INDEX * 8)



/* V6 routing header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V6_RT_HASHABLE_OFST & 7)

#error V6 routing hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_V6_RT_OFST (IPA_MEM_v3_0_RAM_V4_RT_OFST + \

	IPA_MEM_v3_0_RAM_V4_RT_SIZE + IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V6_RT_OFST (IPA_MEM_v3_0_RAM_V6_RT_HASHABLE_OFST + \

	IPA_MEM_v3_0_RAM_V6_RT_HASHABLE_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_V6_NUM_INDEX 15

#define IPA_MEM_v3_0_V6_MODEM_RT_INDEX_LO 0

#define IPA_MEM_v3_0_V6_MODEM_RT_INDEX_HI 6
@@ -304,15 +222,17 @@ 
	(IPA_MEM_v3_0_V6_MODEM_RT_INDEX_HI + 1)

#define IPA_MEM_v3_0_V6_APPS_RT_INDEX_HI \

	(IPA_MEM_v3_0_RAM_V6_NUM_INDEX - 1)

#define IPA_MEM_v3_0_RAM_V6_RT_SIZE (IPA_MEM_v3_0_RAM_V6_NUM_INDEX * 4)

#define IPA_MEM_v3_0_RAM_V6_RT_SIZE \

	(IPA_MEM_v3_0_RAM_V6_NUM_INDEX * 8)



/* V6 routing header table is 8B aligned */

#if (IPA_MEM_v3_0_RAM_V6_RT_OFST & 7)

#error V6 routing header table is not 8B aligned

#error V6 routing non-hashable header table is not 8B aligned

#endif



#define IPA_MEM_v3_0_RAM_MODEM_HDR_OFST (IPA_MEM_v3_0_RAM_V6_RT_OFST + \

	IPA_MEM_v3_0_RAM_V6_RT_SIZE + IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_MODEM_HDR_OFST \

	(IPA_MEM_v3_0_RAM_V6_RT_OFST + \

	IPA_MEM_v3_0_RAM_V6_RT_SIZE + 2 * IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_MODEM_HDR_SIZE 320



/* header table is 8B aligned */
@@ -351,7 +271,7 @@ 


#define IPA_MEM_v3_0_RAM_MODEM_OFST (IPA_MEM_v3_0_RAM_APPS_HDR_PROC_CTX_OFST + \

	IPA_MEM_v3_0_RAM_APPS_HDR_PROC_CTX_SIZE + IPA_MEM_CANARY_SIZE)

#define IPA_MEM_v3_0_RAM_MODEM_SIZE 5800

#define IPA_MEM_v3_0_RAM_MODEM_SIZE 5160



/* modem memory is 4B aligned */

#if (IPA_MEM_v3_0_RAM_MODEM_OFST & 3)
@@ -359,7 +279,7 @@ 
#endif



#define IPA_MEM_v3_0_RAM_APPS_V4_FLT_OFST (IPA_MEM_v3_0_RAM_MODEM_OFST + \

	IPA_MEM_v3_0_RAM_MODEM_SIZE + IPA_MEM_CANARY_SIZE)

	IPA_MEM_v3_0_RAM_MODEM_SIZE)

#define IPA_MEM_v3_0_RAM_APPS_V4_FLT_SIZE 0



/* filtering rule is 4B aligned */

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+106 −14
Original line number Diff line number Diff line
@@ -3451,64 +3451,154 @@ static void ipa_init_mem_partition_v3_0(void) 
	IPA_MEM_PART(ofst_start) = IPA_MEM_v3_0_RAM_OFST_START;

	IPADBG("RAM OFST 0x%x\n", IPA_MEM_PART(ofst_start));



	IPA_MEM_PART(v4_flt_hashable_ofst) =

		IPA_MEM_v3_0_RAM_V4_FLT_HASHABLE_OFST;

	IPA_MEM_PART(v4_flt_hashable_size) =

		IPA_MEM_v3_0_RAM_V4_FLT_HASHABLE_SIZE;

	IPA_MEM_PART(v4_flt_hashable_size_ddr) = IPA_MEM_RAM_V4_FLT_SIZE_DDR;

	IPADBG("V4 FLT HASHABLE OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v4_flt_hashable_ofst),

		IPA_MEM_PART(v4_flt_hashable_size),

		IPA_MEM_PART(v4_flt_hashable_size_ddr));



	IPA_MEM_PART(v4_flt_ofst) = IPA_MEM_v3_0_RAM_V4_FLT_OFST;

	IPA_MEM_PART(v4_flt_size) = IPA_MEM_v3_0_RAM_V4_FLT_SIZE;

	IPA_MEM_PART(v4_flt_size_ddr) = IPA_MEM_RAM_V4_FLT_SIZE_DDR;

	IPADBG("V4 FLT OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n",

	IPADBG("V4 FLT NON-HASHABLE OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v4_flt_ofst), IPA_MEM_PART(v4_flt_size),

		IPA_MEM_PART(v4_flt_size_ddr));



	IPA_MEM_PART(v6_flt_hashable_ofst) =

		IPA_MEM_v3_0_RAM_V6_FLT_HASHABLE_OFST;

	IPA_MEM_PART(v6_flt_hashable_size) =

		IPA_MEM_v3_0_RAM_V6_FLT_HASHABLE_SIZE;

	IPA_MEM_PART(v6_flt_hashable_size_ddr) = IPA_MEM_RAM_V6_FLT_SIZE_DDR;

	IPADBG("V6 FLT HASHABLE OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v6_flt_hashable_ofst),

		IPA_MEM_PART(v6_flt_hashable_size),

		IPA_MEM_PART(v6_flt_hashable_size_ddr));



	IPA_MEM_PART(v6_flt_ofst) = IPA_MEM_v3_0_RAM_V6_FLT_OFST;

	IPA_MEM_PART(v6_flt_size) = IPA_MEM_v3_0_RAM_V6_FLT_SIZE;

	IPA_MEM_PART(v6_flt_size_ddr) = IPA_MEM_RAM_V6_FLT_SIZE_DDR;

	IPADBG("V6 FLT OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n",

	IPADBG("V6 FLT NON-HASHABLE OFST 0x%x SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v6_flt_ofst), IPA_MEM_PART(v6_flt_size),

		IPA_MEM_PART(v6_flt_size_ddr));



	IPA_MEM_PART(v4_rt_hashable_ofst) =

		IPA_MEM_v3_0_RAM_V4_RT_HASHABLE_OFST;

	IPADBG("V4 RT HASHABLE OFST 0x%x\n",

		IPA_MEM_PART(v4_rt_hashable_ofst));



	IPA_MEM_PART(v4_hashable_num_index) =

		IPA_MEM_v3_0_RAM_V4_HASHABLE_NUM_INDEX;

	IPADBG("V4 RT HASHABLE NUM INDEX 0x%x\n",

		IPA_MEM_PART(v4_hashable_num_index));



	IPA_MEM_PART(v4_modem_rt_hashable_index_lo) =

		IPA_MEM_v3_0_V4_MODEM_RT_HASHABLE_INDEX_LO;

	IPA_MEM_PART(v4_modem_rt_hashable_index_hi) =

		IPA_MEM_v3_0_V4_MODEM_RT_HASHABLE_INDEX_HI;

	IPADBG("V4 RT MODEM HASHABLE INDEXES 0x%x - 0x%x\n",

		IPA_MEM_PART(v4_modem_rt_hashable_index_lo),

		IPA_MEM_PART(v4_modem_rt_hashable_index_hi));



	IPA_MEM_PART(v4_apps_rt_hashable_index_lo) =

		IPA_MEM_v3_0_V4_APPS_RT_HASHABLE_INDEX_LO;

	IPA_MEM_PART(v4_apps_rt_hashable_index_hi) =

		IPA_MEM_v3_0_V4_APPS_RT_HASHABLE_INDEX_HI;

	IPADBG("V4 RT APPS HASHABLE INDEXES 0x%x - 0x%x\n",

		IPA_MEM_PART(v4_apps_rt_hashable_index_lo),

		IPA_MEM_PART(v4_apps_rt_hashable_index_hi));



	IPA_MEM_PART(v4_rt_hashable_size) =

		IPA_MEM_v3_0_RAM_V4_RT_HASHABLE_SIZE;

	IPA_MEM_PART(v4_rt_hashable_size_ddr) = IPA_MEM_RAM_V4_RT_SIZE_DDR;

	IPADBG("V4 RT HASHABLE SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v4_rt_hashable_size),

		IPA_MEM_PART(v4_rt_hashable_size_ddr));



	IPA_MEM_PART(v4_rt_ofst) = IPA_MEM_v3_0_RAM_V4_RT_OFST;

	IPADBG("V4 RT OFST 0x%x\n", IPA_MEM_PART(v4_rt_ofst));

	IPADBG("V4 RT NON-HASHABLE OFST 0x%x\n", IPA_MEM_PART(v4_rt_ofst));



	IPA_MEM_PART(v4_num_index) = IPA_MEM_v3_0_RAM_V4_NUM_INDEX;

	IPADBG("V4 RT NUM INDEX 0x%x\n", IPA_MEM_PART(v4_num_index));

	IPADBG("V4 RT NON-HASHABLE NUM INDEX 0x%x\n",

		IPA_MEM_PART(v4_num_index));



	IPA_MEM_PART(v4_modem_rt_index_lo) = IPA_MEM_v3_0_V4_MODEM_RT_INDEX_LO;

	IPA_MEM_PART(v4_modem_rt_index_hi) = IPA_MEM_v3_0_V4_MODEM_RT_INDEX_HI;

	IPADBG("V4 RT MODEM INDEXES 0x%x - 0x%x\n",

	IPADBG("V4 RT MODEM NON-HASHABLE INDEXES 0x%x - 0x%x\n",

		IPA_MEM_PART(v4_modem_rt_index_lo),

		IPA_MEM_PART(v4_modem_rt_index_hi));



	IPA_MEM_PART(v4_apps_rt_index_lo) = IPA_MEM_v3_0_V4_APPS_RT_INDEX_LO;

	IPA_MEM_PART(v4_apps_rt_index_hi) = IPA_MEM_v3_0_V4_APPS_RT_INDEX_HI;

	IPADBG("V4 RT APPS INDEXES 0x%x - 0x%x\n",

	IPADBG("V4 RT APPS NON-HASHABLE INDEXES 0x%x - 0x%x\n",

		IPA_MEM_PART(v4_apps_rt_index_lo),

		IPA_MEM_PART(v4_apps_rt_index_hi));



	IPA_MEM_PART(v4_rt_size) = IPA_MEM_v3_0_RAM_V4_RT_SIZE;

	IPA_MEM_PART(v4_rt_size_ddr) = IPA_MEM_RAM_V4_RT_SIZE_DDR;

	IPADBG("V4 RT SIZE 0x%x DDR SIZE 0x%x\n", IPA_MEM_PART(v4_rt_size),

	IPADBG("V4 RT HASHABLE SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v4_rt_size),

		IPA_MEM_PART(v4_rt_size_ddr));



	IPA_MEM_PART(v6_rt_hashable_ofst) =

		IPA_MEM_v3_0_RAM_V6_RT_HASHABLE_OFST;

	IPADBG("V6 RT HASHABLE OFST 0x%x\n",

		IPA_MEM_PART(v6_rt_hashable_ofst));



	IPA_MEM_PART(v6_hashable_num_index) =

		IPA_MEM_v3_0_RAM_V6_HASHABLE_NUM_INDEX;

	IPADBG("V6 RT HASHABLE NUM INDEX 0x%x\n",

		IPA_MEM_PART(v6_hashable_num_index));



	IPA_MEM_PART(v6_modem_rt_hashable_index_lo) =

		IPA_MEM_v3_0_V6_MODEM_RT_HASHABLE_INDEX_LO;

	IPA_MEM_PART(v6_modem_rt_hashable_index_hi) =

		IPA_MEM_v3_0_V6_MODEM_RT_HASHABLE_INDEX_HI;

	IPADBG("V6 RT MODEM HASHABLE INDEXES 0x%x - 0x%x\n",

		IPA_MEM_PART(v6_modem_rt_hashable_index_lo),

		IPA_MEM_PART(v6_modem_rt_hashable_index_hi));



	IPA_MEM_PART(v6_apps_rt_hashable_index_lo) =

		IPA_MEM_v3_0_V6_APPS_RT_HASHABLE_INDEX_LO;

	IPA_MEM_PART(v6_apps_rt_hashable_index_hi) =

		IPA_MEM_v3_0_V6_APPS_RT_HASHABLE_INDEX_HI;

	IPADBG("V6 RT APPS HASHABLE INDEXES 0x%x - 0x%x\n",

		IPA_MEM_PART(v6_apps_rt_hashable_index_lo),

		IPA_MEM_PART(v6_apps_rt_hashable_index_hi));



	IPA_MEM_PART(v6_rt_hashable_size) =

		IPA_MEM_v3_0_RAM_V6_RT_HASHABLE_SIZE;

	IPA_MEM_PART(v6_rt_hashable_size_ddr) = IPA_MEM_RAM_V6_RT_SIZE_DDR;

	IPADBG("V6 RT HASHABLE SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v6_rt_hashable_size),

		IPA_MEM_PART(v6_rt_hashable_size_ddr));



	IPA_MEM_PART(v6_rt_ofst) = IPA_MEM_v3_0_RAM_V6_RT_OFST;

	IPADBG("V6 RT OFST 0x%x\n", IPA_MEM_PART(v6_rt_ofst));

	IPADBG("V6 RT NON-HASHABLE OFST 0x%x\n", IPA_MEM_PART(v6_rt_ofst));



	IPA_MEM_PART(v6_num_index) = IPA_MEM_v3_0_RAM_V6_NUM_INDEX;

	IPADBG("V6 RT NUM INDEX 0x%x\n", IPA_MEM_PART(v6_num_index));

	IPADBG("V6 RT NON-HASHABLE NUM INDEX 0x%x\n",

		IPA_MEM_PART(v6_num_index));



	IPA_MEM_PART(v6_modem_rt_index_lo) = IPA_MEM_v3_0_V6_MODEM_RT_INDEX_LO;

	IPA_MEM_PART(v6_modem_rt_index_hi) = IPA_MEM_v3_0_V6_MODEM_RT_INDEX_HI;

	IPADBG("V6 RT MODEM INDEXES 0x%x - 0x%x\n",

	IPADBG("V6 RT MODEM NON-HASHABLE INDEXES 0x%x - 0x%x\n",

		IPA_MEM_PART(v6_modem_rt_index_lo),

		IPA_MEM_PART(v6_modem_rt_index_hi));



	IPA_MEM_PART(v6_apps_rt_index_lo) = IPA_MEM_v3_0_V6_APPS_RT_INDEX_LO;

	IPA_MEM_PART(v6_apps_rt_index_hi) = IPA_MEM_v3_0_V6_APPS_RT_INDEX_HI;

	IPADBG("V6 RT APPS INDEXES 0x%x - 0x%x\n",

	IPADBG("V6 RT APPS NON-HASHABLE INDEXES 0x%x - 0x%x\n",

		IPA_MEM_PART(v6_apps_rt_index_lo),

		IPA_MEM_PART(v6_apps_rt_index_hi));



	IPA_MEM_PART(v6_rt_size) = IPA_MEM_v3_0_RAM_V6_RT_SIZE;

	IPA_MEM_PART(v6_rt_size_ddr) = IPA_MEM_RAM_V6_RT_SIZE_DDR;

	IPADBG("V6 RT SIZE 0x%x DDR SIZE 0x%x\n", IPA_MEM_PART(v6_rt_size),

	IPADBG("V6 RT NON-HASHABLE SIZE 0x%x DDR SIZE 0x%x\n",

		IPA_MEM_PART(v6_rt_size),

		IPA_MEM_PART(v6_rt_size_ddr));



	IPA_MEM_PART(modem_hdr_ofst) = IPA_MEM_v3_0_RAM_MODEM_HDR_OFST;
@@ -3550,12 +3640,14 @@ static void ipa_init_mem_partition_v3_0(void) 
	IPA_MEM_PART(apps_v4_flt_ofst) = IPA_MEM_v3_0_RAM_APPS_V4_FLT_OFST;

	IPA_MEM_PART(apps_v4_flt_size) = IPA_MEM_v3_0_RAM_APPS_V4_FLT_SIZE;

	IPADBG("V4 APPS FLT OFST 0x%x SIZE 0x%x\n",

		IPA_MEM_PART(apps_v4_flt_ofst), IPA_MEM_PART(apps_v4_flt_size));

		IPA_MEM_PART(apps_v4_flt_ofst),

		IPA_MEM_PART(apps_v4_flt_size));



	IPA_MEM_PART(apps_v6_flt_ofst) = IPA_MEM_v3_0_RAM_APPS_V6_FLT_OFST;

	IPA_MEM_PART(apps_v6_flt_size) = IPA_MEM_v3_0_RAM_APPS_V6_FLT_SIZE;

	IPADBG("V6 APPS FLT OFST 0x%x SIZE 0x%x\n",

		IPA_MEM_PART(apps_v6_flt_ofst), IPA_MEM_PART(apps_v6_flt_size));

		IPA_MEM_PART(apps_v6_flt_ofst),

		IPA_MEM_PART(apps_v6_flt_size));



	IPA_MEM_PART(end_ofst) = IPA_MEM_v3_0_RAM_END_OFST;

	IPA_MEM_PART(apps_v4_rt_ofst) = IPA_MEM_v3_0_RAM_APPS_V4_RT_OFST;