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Commit f8e6826f authored Mar 26, 2015 by Abhimanyu Kapur Committed by Matt Wagantall May 30, 2015

soc: qcom: Snapshot headers to allow compilation



Snapshot the following headers as of msm-3.14 commit

3bc54cf86bdc7affa7cd4bf7faa3c57fe8f8819d (Merge "msm:
camera: Add dummy sub module in sensor pipeline")

include/linux/irqchip/msm-mpm-irq.h
include/linux/mfd/wcd9xxx/Kbuild
include/linux/mfd/wcd9xxx/core-resource.h
include/linux/mfd/wcd9xxx/core.h
include/linux/mfd/wcd9xxx/pdata.h
include/linux/mfd/wcd9xxx/wcd9310_registers.h
include/linux/mfd/wcd9xxx/wcd9330_registers.h
include/linux/mfd/wcd9xxx/wcd9xxx-slimslave.h
include/linux/mfd/wcd9xxx/wcd9xxx_registers.h
include/linux/msm-bus-board.h
include/linux/msm-bus.h
include/linux/msm_rtb.h
include/linux/regulator/rpm-smd-regulator.h
include/soc/qcom/glink.h
include/soc/qcom/glink_rpm_xprt.h
include/soc/qcom/jtag.h
include/soc/qcom/pm.h
include/soc/qcom/rpm-smd.h
include/soc/qcom/smd.h
include/soc/qcom/smem.h
include/soc/qcom/spm.h

[abhimany: added static inline around few spm functions]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>

fixup! soc: qcom: Snapshot headers to allow compilation

parent 4bf0506a

include/linux/irqchip/msm-mpm-irq.h

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		/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		*/

		#ifndef __MSM_MPM_IRQ_H
		#define __MSM_MPM_IRQ_H

		#include <linux/types.h>
		#include <linux/list.h>

		#define MSM_MPM_NR_MPM_IRQS 64

		#if defined(CONFIG_MSM_MPM_OF)
		/**
		* msm_mpm_enable_pin() - Enable/Disable a MPM pin for idle wakeups.
		*
		* @pin: MPM pin to set
		* @enable: enable/disable the pin
		*
		* returns 0 on success or errorno
		*
		* Drivers can call the function to configure MPM pins for wakeup from idle low
		* power modes. The API provides a direct access to the configuring MPM pins
		* that are not connected to a IRQ/GPIO
		*/
		int msm_mpm_enable_pin(unsigned int pin, unsigned int enable);

		/**
		* msm_mpm_set_pin_wake() - Enable/Disable a MPM pin during suspend
		*
		* @pin: MPM pin to set
		* @enable: enable/disable the pin as wakeup
		*
		* returns 0 on success or errorno
		*
		* Drivers can call the function to configure MPM pins for wakeup from suspend
		* low power modes. The API provides a direct access to the configuring MPM pins
		* that are not connected to a IRQ/GPIO
		*/
		int msm_mpm_set_pin_wake(unsigned int pin, unsigned int on);
		/**
		* msm_mpm_set_pin_type() - Set the flowtype of a MPM pin.
		*
		* @pin: MPM pin to configure
		* @flow_type: flowtype of the MPM pin.
		*
		* returns 0 on success or errorno
		*
		* Drivers can call the function to configure the flowtype of the MPM pins
		* The API provides a direct access to the configuring MPM pins that are not
		* connected to a IRQ/GPIO
		*/
		int msm_mpm_set_pin_type(unsigned int pin, unsigned int flow_type);
		/**
		* msm_mpm_irqs_detectable() - Check if active irqs can be monitored by MPM
		*
		* @from_idle: indicates if the sytem is entering low power mode as a part of
		* suspend/idle task.
		*
		* returns true if all active interrupts can be monitored by the MPM
		*
		* Low power management code calls into this API to check if all active
		* interrupts can be monitored by MPM and choose a level such that all active
		* interrupts can wake the system up from low power mode.
		*/
		bool msm_mpm_irqs_detectable(bool from_idle);
		/**
		* msm_mpm_gpio_detectable() - Check if active gpio irqs can be monitored by
		* MPM
		*
		* @from_idle: indicates if the sytem is entering low power mode as a part of
		* suspend/idle task.
		*
		* returns true if all active GPIO interrupts can be monitored by the MPM
		*
		* Low power management code calls into this API to check if all active
		* GPIO interrupts can be monitored by MPM and choose a level such that all
		* active interrupts can wake the system up from low power mode.
		*/
		bool msm_mpm_gpio_irqs_detectable(bool from_idle);
		/**
		* msm_mpm_enter_sleep() -Called from PM code before entering low power mode
		*
		* @sclk_count: wakeup time in sclk counts for programmed RPM wakeup
		* @from_idle: indicates if the sytem is entering low power mode as a part of
		* suspend/idle task.
		* @cpumask: the next cpu to wakeup.
		*
		* Low power management code calls into this API to configure the MPM to
		* monitor the active irqs before going to sleep.
		*/
		void msm_mpm_enter_sleep(uint32_t sclk_count, bool from_idle,
		const struct cpumask *cpumask);
		/**
		* msm_mpm_exit_sleep() -Called from PM code after resuming from low power mode
		*
		* @from_idle: indicates if the sytem is entering low power mode as a part of
		* suspend/idle task.
		*
		* Low power management code calls into this API to query the MPM for the
		* wakeup source and retriggering the appropriate interrupt.
		*/
		void msm_mpm_exit_sleep(bool from_idle);
		/**
		* of_mpm_init() - Device tree initialization function
		*
		* The initialization function is called after * GPIO/GIC device initialization
		* routines are called and before any device irqs are requested. MPM driver
		* keeps track of all enabled/wakeup interrupts in the system to be able to
		* configure MPM when entering a system wide low power mode. The MPM is a
		* alway-on low power hardware block that monitors 64 wakeup interrupts when the
		* system is in a low power mode. The initialization function constructs the MPM
		* mapping between the IRQs and the MPM pin based on data in the device tree.
		*/
		void __init of_mpm_init(void);
		#else
		static inline int msm_mpm_enable_irq(unsigned int irq, unsigned int enable)
		{ return -ENODEV; }
		static inline int msm_mpm_set_irq_wake(unsigned int irq, unsigned int on)
		{ return -ENODEV; }
		static inline int msm_mpm_set_irq_type(unsigned int irq, unsigned int flow_type)
		{ return -ENODEV; }
		static inline int msm_mpm_enable_pin(unsigned int pin, unsigned int enable)
		{ return -ENODEV; }
		static inline int msm_mpm_set_pin_wake(unsigned int pin, unsigned int on)
		{ return -ENODEV; }
		static inline int msm_mpm_set_pin_type(unsigned int pin,
		unsigned int flow_type)
		{ return -ENODEV; }
		static inline bool msm_mpm_irqs_detectable(bool from_idle)
		{ return false; }
		static inline bool msm_mpm_gpio_irqs_detectable(bool from_idle)
		{ return false; }
		static inline void msm_mpm_enter_sleep(uint32_t sclk_count, bool from_idle,
		const struct cpumask *cpumask) {}
		static inline void msm_mpm_exit_sleep(bool from_idle) {}
		static inline void __init of_mpm_init(void) {}
		#endif
		#ifdef CONFIG_MSM_MPM_OF
		/** msm_mpm_suspend_prepare() - Called at prepare_late() op during suspend
		*
		*
		* When called the MPM driver checks if the wakeup interrupts can be monitored
		* by MPM hardware and program them accordingly. If wake up interrupts cannot
		* be monitored then it disallows system low power modes.
		*/
		void msm_mpm_suspend_prepare(void);
		/** msm_mpm_suspend_wake - Called during wake() op in suspend.
		*
		* When called MPM drivers sets the vote for system low power modes depending
		* on the active interrupts.
		*/
		void msm_mpm_suspend_wake(void);
		#else
		static inline void msm_mpm_suspend_prepare(void) {}
		static inline void msm_mpm_suspend_wake(void) {}
		#endif
		#endif /* __MSM_MPM_IRQ_H */

include/linux/mfd/wcd9xxx/Kbuild

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		header-y += wcd9xxx_registers.h
		header-y += wcd9320_registers.h

include/linux/mfd/wcd9xxx/core-resource.h

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		/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#ifndef __MFD_CORE_RESOURCE_H__
		#define __MFD_CORE_RESOURCE_H__

		#include <linux/types.h>
		#include <linux/interrupt.h>
		#include <linux/pm_qos.h>

		#define WCD9XXX_MAX_IRQ_REGS 4
		#define WCD9XXX_MAX_NUM_IRQS (WCD9XXX_MAX_IRQ_REGS * 8)

		struct intr_data {
		int intr_num;
		bool clear_first;
		};

		enum wcd9xxx_pm_state {
		WCD9XXX_PM_SLEEPABLE,
		WCD9XXX_PM_AWAKE,
		WCD9XXX_PM_ASLEEP,
		};

		enum {
		WCD9XXX_INTR_STATUS_BASE = 0,
		WCD9XXX_INTR_CLEAR_BASE,
		WCD9XXX_INTR_MASK_BASE,
		WCD9XXX_INTR_LEVEL_BASE,
		WCD9XXX_INTR_CLR_COMMIT,
		WCD9XXX_INTR_REG_MAX,
		};

		enum wcd9xxx_intf_status {
		WCD9XXX_INTERFACE_TYPE_PROBING,
		WCD9XXX_INTERFACE_TYPE_SLIMBUS,
		WCD9XXX_INTERFACE_TYPE_I2C,
		};

		struct wcd9xxx_core_resource {
		struct mutex irq_lock;
		struct mutex nested_irq_lock;

		enum wcd9xxx_pm_state pm_state;
		struct mutex pm_lock;
		/* pm_wq notifies change of pm_state */
		wait_queue_head_t pm_wq;
		struct pm_qos_request pm_qos_req;
		int wlock_holders;


		/* holds the table of interrupts per codec */
		const struct intr_data *intr_table;
		int intr_table_size;
		unsigned int irq_base;
		unsigned int irq;
		u8 irq_masks_cur[WCD9XXX_MAX_IRQ_REGS];
		u8 irq_masks_cache[WCD9XXX_MAX_IRQ_REGS];
		bool irq_level_high[WCD9XXX_MAX_NUM_IRQS];
		int num_irqs;
		int num_irq_regs;
		u16 intr_reg[WCD9XXX_INTR_REG_MAX];

		/* Callback functions to read/write codec registers */
		int (codec_reg_read) (struct wcd9xxx_core_resource ,
		unsigned short);
		int (codec_reg_write) (struct wcd9xxx_core_resource ,
		unsigned short, u8);
		int (codec_bulk_read) (struct wcd9xxx_core_resource ,
		unsigned short, int, u8 *);
		int (codec_bulk_write) (struct wcd9xxx_core_resource ,
		unsigned short, int, u8 *);

		/* Pointer to parent container data structure */
		void *parent;

		struct device *dev;
		};

		extern int wcd9xxx_core_res_init(
		struct wcd9xxx_core_resource*,
		int, int,
		int (codec_read)(struct wcd9xxx_core_resource , unsigned short),
		int (codec_write)(struct wcd9xxx_core_resource , unsigned short, u8),
		int (codec_bulk_read) (struct wcd9xxx_core_resource , unsigned short,
		int, u8 *),
		int (codec_bulk_write) (struct wcd9xxx_core_resource , unsigned short,
		int, u8 *));

		extern void wcd9xxx_core_res_deinit(
		struct wcd9xxx_core_resource *);

		extern int wcd9xxx_core_res_suspend(
		struct wcd9xxx_core_resource *,
		pm_message_t);

		extern int wcd9xxx_core_res_resume(
		struct wcd9xxx_core_resource *);

		extern int wcd9xxx_core_irq_init(
		struct wcd9xxx_core_resource*);

		extern int wcd9xxx_initialize_irq(
		struct wcd9xxx_core_resource*,
		unsigned int,
		unsigned int);

		enum wcd9xxx_intf_status wcd9xxx_get_intf_type(void);
		void wcd9xxx_set_intf_type(enum wcd9xxx_intf_status);

		bool wcd9xxx_lock_sleep(struct wcd9xxx_core_resource *);
		void wcd9xxx_unlock_sleep(struct wcd9xxx_core_resource *);
		void wcd9xxx_nested_irq_lock(struct wcd9xxx_core_resource *);
		void wcd9xxx_nested_irq_unlock(struct wcd9xxx_core_resource *);
		enum wcd9xxx_pm_state wcd9xxx_pm_cmpxchg(
		struct wcd9xxx_core_resource *,
		enum wcd9xxx_pm_state,
		enum wcd9xxx_pm_state);

		int wcd9xxx_request_irq(struct wcd9xxx_core_resource *, int,
		irq_handler_t, const char , void );

		void wcd9xxx_free_irq(struct wcd9xxx_core_resource , int, void);
		void wcd9xxx_enable_irq(struct wcd9xxx_core_resource *, int);
		void wcd9xxx_disable_irq(struct wcd9xxx_core_resource *, int);
		void wcd9xxx_disable_irq_sync(struct wcd9xxx_core_resource *, int);
		int wcd9xxx_reg_read(struct wcd9xxx_core_resource *,
		unsigned short);
		int wcd9xxx_reg_write(struct wcd9xxx_core_resource *,
		unsigned short, u8);
		int wcd9xxx_bulk_read(struct wcd9xxx_core_resource *,
		unsigned short, int, u8 *);
		int wcd9xxx_bulk_write(struct wcd9xxx_core_resource*,
		unsigned short, int, u8*);
		int wcd9xxx_reg_update_bits(struct wcd9xxx_core_resource *core_res,
		unsigned short reg, u8 mask, u8 val);
		int wcd9xxx_irq_init(struct wcd9xxx_core_resource *);
		void wcd9xxx_irq_exit(struct wcd9xxx_core_resource *);
		int wcd9xxx_core_res_resume(
		struct wcd9xxx_core_resource *);
		int wcd9xxx_core_res_suspend(
		struct wcd9xxx_core_resource *,
		pm_message_t);
		#endif

include/linux/mfd/wcd9xxx/core.h

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		/* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#ifndef __MFD_TABLA_CORE_H__
		#define __MFD_TABLA_CORE_H__

		#include <linux/types.h>
		#include <linux/platform_device.h>
		#include <linux/of_irq.h>
		#include <linux/mfd/wcd9xxx/core-resource.h>


		#define WCD9XXX_SLIM_NUM_PORT_REG 3
		#define TABLA_VERSION_1_0 0
		#define TABLA_VERSION_1_1 1
		#define TABLA_VERSION_2_0 2
		#define TABLA_IS_1_X(ver) \
		(((ver == TABLA_VERSION_1_0) \|\| (ver == TABLA_VERSION_1_1)) ? 1 : 0)
		#define TABLA_IS_2_0(ver) ((ver == TABLA_VERSION_2_0) ? 1 : 0)

		#define WCD9XXX_SUPPLY_BUCK_NAME "cdc-vdd-buck"

		#define SITAR_VERSION_1P0 0
		#define SITAR_VERSION_1P1 1
		#define SITAR_IS_1P0(ver) \
		((ver == SITAR_VERSION_1P0) ? 1 : 0)
		#define SITAR_IS_1P1(ver) \
		((ver == SITAR_VERSION_1P1) ? 1 : 0)

		#define TAIKO_VERSION_1_0 1
		#define TAIKO_IS_1_0(ver) \
		((ver == TAIKO_VERSION_1_0) ? 1 : 0)

		#define TAPAN_VERSION_1_0 0
		#define TAPAN_IS_1_0(ver) \
		((ver == TAPAN_VERSION_1_0) ? 1 : 0)

		#define TOMTOM_VERSION_1_0 1
		#define TOMTOM_IS_1_0(ver) \
		((ver == TOMTOM_VERSION_1_0) ? 1 : 0)

		enum wcd9xxx_slim_slave_addr_type {
		WCD9XXX_SLIM_SLAVE_ADDR_TYPE_TABLA,
		WCD9XXX_SLIM_SLAVE_ADDR_TYPE_TAIKO,
		};

		enum codec_variant {
		WCD9XXX,
		WCD9330,
		WCD9335,
		};

		enum {
		/* INTR_REG 0 */
		WCD9XXX_IRQ_SLIMBUS = 0,
		WCD9XXX_IRQ_MBHC_REMOVAL,
		WCD9XXX_IRQ_MBHC_SHORT_TERM,
		WCD9XXX_IRQ_MBHC_PRESS,
		WCD9XXX_IRQ_MBHC_RELEASE,
		WCD9XXX_IRQ_MBHC_POTENTIAL,
		WCD9XXX_IRQ_MBHC_INSERTION,
		WCD9XXX_IRQ_BG_PRECHARGE,
		/* INTR_REG 1 */
		WCD9XXX_IRQ_PA1_STARTUP,
		WCD9XXX_IRQ_PA2_STARTUP,
		WCD9XXX_IRQ_PA3_STARTUP,
		WCD9XXX_IRQ_PA4_STARTUP,
		WCD9306_IRQ_HPH_PA_OCPR_FAULT = WCD9XXX_IRQ_PA4_STARTUP,
		WCD9XXX_IRQ_PA5_STARTUP,
		WCD9XXX_IRQ_MICBIAS1_PRECHARGE,
		WCD9306_IRQ_HPH_PA_OCPL_FAULT = WCD9XXX_IRQ_MICBIAS1_PRECHARGE,
		WCD9XXX_IRQ_MICBIAS2_PRECHARGE,
		WCD9XXX_IRQ_MICBIAS3_PRECHARGE,
		/* INTR_REG 2 */
		WCD9XXX_IRQ_HPH_PA_OCPL_FAULT,
		WCD9XXX_IRQ_HPH_PA_OCPR_FAULT,
		WCD9XXX_IRQ_EAR_PA_OCPL_FAULT,
		WCD9XXX_IRQ_HPH_L_PA_STARTUP,
		WCD9XXX_IRQ_HPH_R_PA_STARTUP,
		WCD9320_IRQ_EAR_PA_STARTUP,
		WCD9306_IRQ_MBHC_JACK_SWITCH = WCD9320_IRQ_EAR_PA_STARTUP,
		WCD9310_NUM_IRQS,
		WCD9XXX_IRQ_RESERVED_0 = WCD9310_NUM_IRQS,
		WCD9XXX_IRQ_RESERVED_1,
		WCD9330_IRQ_SVASS_ERR_EXCEPTION = WCD9310_NUM_IRQS,
		WCD9330_IRQ_MBHC_JACK_SWITCH,
		/* INTR_REG 3 */
		WCD9XXX_IRQ_MAD_AUDIO,
		WCD9XXX_IRQ_MAD_ULTRASOUND,
		WCD9XXX_IRQ_MAD_BEACON,
		WCD9XXX_IRQ_SPEAKER_CLIPPING,
		WCD9320_IRQ_MBHC_JACK_SWITCH,
		WCD9306_NUM_IRQS,
		WCD9XXX_IRQ_VBAT_MONITOR_ATTACK = WCD9306_NUM_IRQS,
		WCD9XXX_IRQ_VBAT_MONITOR_RELEASE,
		WCD9XXX_NUM_IRQS,
		/* WCD9330 INTR1_REG 3*/
		WCD9330_IRQ_SVASS_ENGINE = WCD9XXX_IRQ_MAD_AUDIO,
		WCD9330_IRQ_MAD_AUDIO,
		WCD9330_IRQ_MAD_ULTRASOUND,
		WCD9330_IRQ_MAD_BEACON,
		WCD9330_IRQ_SPEAKER1_CLIPPING,
		WCD9330_IRQ_SPEAKER2_CLIPPING,
		WCD9330_IRQ_VBAT_MONITOR_ATTACK,
		WCD9330_IRQ_VBAT_MONITOR_RELEASE,
		WCD9330_NUM_IRQS,
		WCD9XXX_IRQ_RESERVED_2 = WCD9330_NUM_IRQS,
		};

		enum {
		/* INTR_REG 0 */
		WCD9335_IRQ_FLL_LOCK_LOSS = 1,
		WCD9335_IRQ_HPH_PA_OCPL_FAULT,
		WCD9335_IRQ_HPH_PA_OCPR_FAULT,
		WCD9335_IRQ_EAR_PA_OCP_FAULT,
		WCD9335_IRQ_HPH_PA_CNPL_COMPLETE,
		WCD9335_IRQ_HPH_PA_CNPR_COMPLETE,
		WCD9335_IRQ_EAR_PA_CNP_COMPLETE,
		/* INTR_REG 1 */
		WCD9335_IRQ_MBHC_SW_DET,
		WCD9335_IRQ_MBHC_ELECT_INS_REM_DET,
		WCD9335_IRQ_MBHC_BUTTON_PRESS_DET,
		WCD9335_IRQ_MBHC_BUTTON_RELEASE_DET,
		WCD9335_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
		WCD9335_IRQ_RESERVED_0,
		WCD9335_IRQ_RESERVED_1,
		WCD9335_IRQ_RESERVED_2,
		/* INTR_REG 2 */
		WCD9335_IRQ_LINE_PA1_CNP_COMPLETE,
		WCD9335_IRQ_LINE_PA2_CNP_COMPLETE,
		WCD9335_IRQ_LINE_PA3_CNP_COMPLETE,
		WCD9335_IRQ_LINE_PA4_CNP_COMPLETE,
		WCD9335_IRQ_SOUNDWIRE,
		WCD9335_IRQ_VDD_DIG_RAMP_COMPLETE,
		WCD9335_IRQ_RCO_ERROR,
		WCD9335_IRQ_SVA_ERROR,
		/* INTR_REG 3 */
		WCD9335_IRQ_MAD_AUDIO,
		WCD9335_IRQ_MAD_BEACON,
		WCD9335_IRQ_MAD_ULTRASOUND,
		WCD9335_IRQ_VBAT_ATTACK,
		WCD9335_IRQ_VBAT_RESTORE,
		WCD9335_IRQ_SVA_OUTBOX1,
		WCD9335_IRQ_SVA_OUTBOX2,
		WCD9335_NUM_IRQS,
		};

		enum {
		TABLA_NUM_IRQS = WCD9310_NUM_IRQS,
		SITAR_NUM_IRQS = WCD9310_NUM_IRQS,
		TAIKO_NUM_IRQS = WCD9XXX_NUM_IRQS,
		TAPAN_NUM_IRQS = WCD9306_NUM_IRQS,
		TOMTOM_NUM_IRQS = WCD9330_NUM_IRQS,
		TASHA_NUM_IRQS = WCD9335_NUM_IRQS,
		};

		/*
		* data structure for Slimbus and I2S channel.
		* Some of fields are only used in smilbus mode
		*/
		struct wcd9xxx_ch {
		u32 sph; /* share channel handle - slimbus only */
		u32 ch_num; /*
		* vitrual channel number, such as 128 -144.
		* apply for slimbus only
		*/
		u16 ch_h; /* chanel handle - slimbus only */
		u16 port; /*
		* tabla port for RX and TX
		* such as 0-9 for TX and 10 -16 for RX
		* apply for both i2s and slimbus
		*/
		u16 shift; /*
		* shift bit for RX and TX
		* apply for both i2s and slimbus
		*/
		struct list_head list; /*
		* channel link list
		* apply for both i2s and slimbus
		*/
		};

		struct wcd9xxx_codec_dai_data {
		u32 rate; /* sample rate */
		u32 bit_width; /* sit width 16,24,32 */
		struct list_head wcd9xxx_ch_list; /* channel list */
		u16 grph; /* slimbus group handle */
		unsigned long ch_mask;
		wait_queue_head_t dai_wait;
		bool bus_down_in_recovery;
		};

		#define WCD9XXX_CH(xport, xshift) \
		{.port = xport, .shift = xshift}

		enum wcd9xxx_chipid_major {
		TABLA_MAJOR = cpu_to_le16(0x100),
		SITAR_MAJOR = cpu_to_le16(0x101),
		TAIKO_MAJOR = cpu_to_le16(0x102),
		TAPAN_MAJOR = cpu_to_le16(0x103),
		TOMTOM_MAJOR = cpu_to_le16(0x105),
		TASHA_MAJOR = cpu_to_le16(0x107),
		};

		struct wcd9xxx_codec_type {
		u16 id_major;
		u16 id_minor;
		struct mfd_cell *dev;
		int size;
		int num_irqs;
		int version; /* -1 to retrive version from chip version register */
		enum wcd9xxx_slim_slave_addr_type slim_slave_type;
		u16 i2c_chip_status;
		};

		struct wcd9xxx {
		struct device *dev;
		struct slim_device *slim;
		struct slim_device *slim_slave;
		struct mutex io_lock;
		struct mutex xfer_lock;
		u8 version;

		int reset_gpio;

		int (read_dev)(struct wcd9xxx wcd9xxx, unsigned short reg,
		int bytes, void *dest, bool interface_reg);
		int (write_dev)(struct wcd9xxx wcd9xxx, unsigned short reg,
		int bytes, void *src, bool interface_reg);
		int (dev_down)(struct wcd9xxx wcd9xxx);
		int (post_reset)(struct wcd9xxx wcd9xxx);

		void *ssr_priv;
		bool slim_device_bootup;

		u32 num_of_supplies;
		struct regulator_bulk_data *supplies;

		struct wcd9xxx_core_resource core_res;

		u16 id_minor;
		u16 id_major;

		/* Slimbus or I2S port */
		u32 num_rx_port;
		u32 num_tx_port;
		struct wcd9xxx_ch *rx_chs;
		struct wcd9xxx_ch *tx_chs;
		u32 mclk_rate;
		enum codec_variant type;
		bool using_regmap;
		struct regmap *regmap;

		const struct wcd9xxx_codec_type *codec_type;
		bool prev_pg_valid;
		u8 prev_pg;
		};

		int wcd9xxx_interface_reg_read(struct wcd9xxx *wcd9xxx, unsigned short reg);
		int wcd9xxx_interface_reg_write(struct wcd9xxx *wcd9xxx, unsigned short reg,
		u8 val);
		int wcd9xxx_get_logical_addresses(u8 pgd_la, u8 inf_la);
		int wcd9xxx_slim_write_repeat(struct wcd9xxx *wcd9xxx, unsigned short reg,
		int bytes, void *src);
		int wcd9xxx_slim_reserve_bw(struct wcd9xxx *wcd9xxx,
		u32 bw_ops, bool commit);

		#if defined(CONFIG_WCD9310_CODEC) \|\| \
		defined(CONFIG_WCD9304_CODEC) \|\| \
		defined(CONFIG_WCD9320_CODEC) \|\| \
		defined(CONFIG_WCD9330_CODEC) \|\| \
		defined(CONFIG_WCD9335_CODEC) \|\| \
		defined(CONFIG_WCD9306_CODEC)
		int __init wcd9xxx_irq_of_init(struct device_node *node,
		struct device_node *parent);
		#else
		static inline int __init wcd9xxx_irq_of_init(struct device_node *node,
		struct device_node *parent)
		{
		return 0;
		}
		#endif /* CONFIG_OF */
		static inline void wcd9xxx_reg_update(struct wcd9xxx *core,
		unsigned short reg,
		u8 mask, u8 val)
		{
		u8 reg_val;

		if (core) {
		reg_val = wcd9xxx_reg_read(&core->core_res, reg);
		reg_val = (reg_val & ~mask) \| (val & mask);
		wcd9xxx_reg_write(&core->core_res, reg, reg_val);
		}
		}
		#endif

include/linux/mfd/wcd9xxx/pdata.h

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		/* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#ifndef __MFD_TABLA_PDATA_H__

		#define __MFD_TABLA_PDATA_H__

		#include <linux/slimbus/slimbus.h>

		#define MICBIAS_EXT_BYP_CAP 0x00
		#define MICBIAS_NO_EXT_BYP_CAP 0x01

		#define SITAR_LDOH_1P95_V 0x0
		#define SITAR_LDOH_2P35_V 0x1
		#define SITAR_LDOH_2P75_V 0x2
		#define SITAR_LDOH_2P85_V 0x3

		#define SITAR_CFILT1_SEL 0x0
		#define SITAR_CFILT2_SEL 0x1
		#define SITAR_CFILT3_SEL 0x2

		#define WCD9XXX_LDOH_1P95_V 0x0
		#define WCD9XXX_LDOH_2P35_V 0x1
		#define WCD9XXX_LDOH_2P75_V 0x2
		#define WCD9XXX_LDOH_2P85_V 0x3
		#define WCD9XXX_LDOH_3P0_V 0x3

		#define TABLA_LDOH_1P95_V 0x0
		#define TABLA_LDOH_2P35_V 0x1
		#define TABLA_LDOH_2P75_V 0x2
		#define TABLA_LDOH_2P85_V 0x3

		#define TABLA_CFILT1_SEL 0x0
		#define TABLA_CFILT2_SEL 0x1
		#define TABLA_CFILT3_SEL 0x2

		#define MAX_AMIC_CHANNEL 7

		#define TABLA_OCP_300_MA 0x0
		#define TABLA_OCP_350_MA 0x2
		#define TABLA_OCP_365_MA 0x3
		#define TABLA_OCP_150_MA 0x4
		#define TABLA_OCP_190_MA 0x6
		#define TABLA_OCP_220_MA 0x7

		#define TABLA_DCYCLE_255 0x0
		#define TABLA_DCYCLE_511 0x1
		#define TABLA_DCYCLE_767 0x2
		#define TABLA_DCYCLE_1023 0x3
		#define TABLA_DCYCLE_1279 0x4
		#define TABLA_DCYCLE_1535 0x5
		#define TABLA_DCYCLE_1791 0x6
		#define TABLA_DCYCLE_2047 0x7
		#define TABLA_DCYCLE_2303 0x8
		#define TABLA_DCYCLE_2559 0x9
		#define TABLA_DCYCLE_2815 0xA
		#define TABLA_DCYCLE_3071 0xB
		#define TABLA_DCYCLE_3327 0xC
		#define TABLA_DCYCLE_3583 0xD
		#define TABLA_DCYCLE_3839 0xE
		#define TABLA_DCYCLE_4095 0xF

		#define WCD9XXX_MCLK_CLK_12P288MHZ 12288000
		#define WCD9XXX_MCLK_CLK_9P6HZ 9600000

		/* Only valid for 9.6 MHz mclk */
		#define WCD9XXX_DMIC_SAMPLE_RATE_600KHZ 600000
		#define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
		#define WCD9XXX_DMIC_SAMPLE_RATE_3P2MHZ 3200000
		#define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000

		/* Only valid for 12.288 MHz mclk */
		#define WCD9XXX_DMIC_SAMPLE_RATE_768KHZ 768000
		#define WCD9XXX_DMIC_SAMPLE_RATE_2P048MHZ 2048000
		#define WCD9XXX_DMIC_SAMPLE_RATE_3P072MHZ 3072000
		#define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
		#define WCD9XXX_DMIC_SAMPLE_RATE_6P144MHZ 6144000

		#define WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED 0

		struct wcd9xxx_amic {
		/*legacy mode, txfe_enable and txfe_buff take 7 input
		* each bit represent the channel / TXFE number
		* and numbered as below
		* bit 0 = channel 1 / TXFE1_ENABLE / TXFE1_BUFF
		* bit 1 = channel 2 / TXFE2_ENABLE / TXFE2_BUFF
		* ...
		* bit 7 = channel 7 / TXFE7_ENABLE / TXFE7_BUFF
		*/
		u8 legacy_mode:MAX_AMIC_CHANNEL;
		u8 txfe_enable:MAX_AMIC_CHANNEL;
		u8 txfe_buff:MAX_AMIC_CHANNEL;
		u8 use_pdata:MAX_AMIC_CHANNEL;
		};

		/* Each micbias can be assigned to one of three cfilters
		* Vbatt_min >= .15V + ldoh_v
		* ldoh_v >= .15v + cfiltx_mv
		* If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv
		* If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv
		* If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv
		* If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv
		*/

		struct wcd9xxx_micbias_setting {
		u8 ldoh_v;
		u32 cfilt1_mv; /* in mv */
		u32 cfilt2_mv; /* in mv */
		u32 cfilt3_mv; /* in mv */
		u32 micb1_mv;
		u32 micb2_mv;
		u32 micb3_mv;
		u32 micb4_mv;
		/* Different WCD9xxx series codecs may not
		* have 4 mic biases. If a codec has fewer
		* mic biases, some of these properties will
		* not be used.
		*/
		u8 bias1_cfilt_sel;
		u8 bias2_cfilt_sel;
		u8 bias3_cfilt_sel;
		u8 bias4_cfilt_sel;
		u8 bias1_cap_mode;
		u8 bias2_cap_mode;
		u8 bias3_cap_mode;
		u8 bias4_cap_mode;
		bool bias2_is_headset_only;
		};

		struct wcd9xxx_ocp_setting {
		unsigned int use_pdata:1; /* 0 - use sys default as recommended */
		unsigned int num_attempts:4; /* up to 15 attempts */
		unsigned int run_time:4; /* in duty cycle */
		unsigned int wait_time:4; /* in duty cycle */
		unsigned int hph_ocp_limit:3; /* Headphone OCP current limit */
		};

		#define WCD9XXX_MAX_REGULATOR 9
		/*
		* format : TABLA_<POWER_SUPPLY_PIN_NAME>_CUR_MAX
		*
		* <POWER_SUPPLY_PIN_NAME> from Tabla objective spec
		*/

		#define WCD9XXX_CDC_VDDA_CP_CUR_MAX 500000
		#define WCD9XXX_CDC_VDDA_RX_CUR_MAX 20000
		#define WCD9XXX_CDC_VDDA_TX_CUR_MAX 20000
		#define WCD9XXX_VDDIO_CDC_CUR_MAX 5000

		#define WCD9XXX_VDDD_CDC_D_CUR_MAX 5000
		#define WCD9XXX_VDDD_CDC_A_CUR_MAX 5000

		#define WCD9XXX_VDD_SPKDRV_NAME "cdc-vdd-spkdrv"
		#define WCD9XXX_VDD_SPKDRV2_NAME "cdc-vdd-spkdrv-2"

		struct wcd9xxx_regulator {
		const char *name;
		int min_uV;
		int max_uV;
		int optimum_uA;
		bool ondemand;
		struct regulator *regulator;
		};

		struct wcd9xxx_pdata {
		int irq;
		int irq_base;
		int num_irqs;
		int reset_gpio;
		struct wcd9xxx_amic amic_settings;
		struct slim_device slimbus_slave_device;
		struct wcd9xxx_micbias_setting micbias;
		struct wcd9xxx_ocp_setting ocp;
		struct wcd9xxx_regulator regulator[WCD9XXX_MAX_REGULATOR];
		u32 mclk_rate;
		u32 dmic_sample_rate;
		u32 mad_dmic_sample_rate;
		enum codec_variant cdc_variant;
		u16 use_pinctrl;
		};

		#endif