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Commit f867c60d authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: gfx init fixes for r6xx/r7xx 



This fixes some issues with the last gfx init patch.

Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 57f50d70

drivers/gpu/drm/radeon/r600.c

+1 −0
Original line number Diff line number Diff line
@@ -1133,6 +1133,7 @@ void r600_gpu_init(struct radeon_device *rdev) 
	/* Setup pipes */

	WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);

	WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);

	WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);



	tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);

	WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);

drivers/gpu/drm/radeon/r600_cp.c

+3 −0
Original line number Diff line number Diff line
@@ -1548,10 +1548,13 @@ static void r700_gfx_init(struct drm_device *dev, 


	RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);

	RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);

	RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);



	RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);

	RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);

	RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);

	RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);

	RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);



	num_qd_pipes =

		R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8);

drivers/gpu/drm/radeon/rv770.c

+3 −0
Original line number Diff line number Diff line
@@ -648,10 +648,13 @@ static void rv770_gpu_init(struct radeon_device *rdev) 


	WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);

	WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);

	WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);

	WREG32(CC_SYS_RB_BACKEND_DISABLE,  cc_rb_backend_disable);



	WREG32(CGTS_SYS_TCC_DISABLE, 0);

	WREG32(CGTS_TCC_DISABLE, 0);

	WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);

	WREG32(CGTS_USER_TCC_DISABLE, 0);



	num_qd_pipes =

		R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);