Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next (f85b02c2) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/net/ethernet/intel/igb/e1000_82575.c

+265 −223

Original line number	Original line	Diff line number	Diff line
	@@ -111,162 +111,146 @@ static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
	return ext_mdio;		return ext_mdio;
	}		}

	static s32 igb_get_invariants_82575(struct e1000_hw *hw)		/**
			* igb_init_phy_params_82575 - Init PHY func ptrs.
			* @hw: pointer to the HW structure
			**/
			static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
	{		{
	struct e1000_phy_info *phy = &hw->phy;		struct e1000_phy_info *phy = &hw->phy;
	struct e1000_nvm_info *nvm = &hw->nvm;		s32 ret_val = 0;
	struct e1000_mac_info *mac = &hw->mac;		u32 ctrl_ext;
	struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
	u32 eecd;
	s32 ret_val;
	u16 size;
	u32 ctrl_ext = 0;

	switch (hw->device_id) {		if (hw->phy.media_type != e1000_media_type_copper) {
	case E1000_DEV_ID_82575EB_COPPER:		phy->type = e1000_phy_none;
	case E1000_DEV_ID_82575EB_FIBER_SERDES:		goto out;
	case E1000_DEV_ID_82575GB_QUAD_COPPER:
	mac->type = e1000_82575;
	break;
	case E1000_DEV_ID_82576:
	case E1000_DEV_ID_82576_NS:
	case E1000_DEV_ID_82576_NS_SERDES:
	case E1000_DEV_ID_82576_FIBER:
	case E1000_DEV_ID_82576_SERDES:
	case E1000_DEV_ID_82576_QUAD_COPPER:
	case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
	case E1000_DEV_ID_82576_SERDES_QUAD:
	mac->type = e1000_82576;
	break;
	case E1000_DEV_ID_82580_COPPER:
	case E1000_DEV_ID_82580_FIBER:
	case E1000_DEV_ID_82580_QUAD_FIBER:
	case E1000_DEV_ID_82580_SERDES:
	case E1000_DEV_ID_82580_SGMII:
	case E1000_DEV_ID_82580_COPPER_DUAL:
	case E1000_DEV_ID_DH89XXCC_SGMII:
	case E1000_DEV_ID_DH89XXCC_SERDES:
	case E1000_DEV_ID_DH89XXCC_BACKPLANE:
	case E1000_DEV_ID_DH89XXCC_SFP:
	mac->type = e1000_82580;
	break;
	case E1000_DEV_ID_I350_COPPER:
	case E1000_DEV_ID_I350_FIBER:
	case E1000_DEV_ID_I350_SERDES:
	case E1000_DEV_ID_I350_SGMII:
	mac->type = e1000_i350;
	break;
	case E1000_DEV_ID_I210_COPPER:
	case E1000_DEV_ID_I210_COPPER_OEM1:
	case E1000_DEV_ID_I210_COPPER_IT:
	case E1000_DEV_ID_I210_FIBER:
	case E1000_DEV_ID_I210_SERDES:
	case E1000_DEV_ID_I210_SGMII:
	mac->type = e1000_i210;
	break;
	case E1000_DEV_ID_I211_COPPER:
	mac->type = e1000_i211;
	break;
	default:
	return -E1000_ERR_MAC_INIT;
	break;
	}		}

	/* Set media type */		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
	/*		phy->reset_delay_us = 100;
	* The 82575 uses bits 22:23 for link mode. The mode can be changed
	* based on the EEPROM. We cannot rely upon device ID. There
	* is no distinguishable difference between fiber and internal
	* SerDes mode on the 82575. There can be an external PHY attached
	* on the SGMII interface. For this, we'll set sgmii_active to true.
	*/
	phy->media_type = e1000_media_type_copper;
	dev_spec->sgmii_active = false;

	ctrl_ext = rd32(E1000_CTRL_EXT);		ctrl_ext = rd32(E1000_CTRL_EXT);
	switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
	case E1000_CTRL_EXT_LINK_MODE_SGMII:		if (igb_sgmii_active_82575(hw)) {
	dev_spec->sgmii_active = true;		phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
			ctrl_ext \|= E1000_CTRL_I2C_ENA;
			} else {
			phy->ops.reset = igb_phy_hw_reset;
			ctrl_ext &= ~E1000_CTRL_I2C_ENA;
			}

			wr32(E1000_CTRL_EXT, ctrl_ext);
			igb_reset_mdicnfg_82580(hw);

			if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
			phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
			phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
			} else {
			switch (hw->mac.type) {
			case e1000_82580:
			case e1000_i350:
			phy->ops.read_reg = igb_read_phy_reg_82580;
			phy->ops.write_reg = igb_write_phy_reg_82580;
	break;		break;
	case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:		case e1000_i210:
	case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:		case e1000_i211:
	hw->phy.media_type = e1000_media_type_internal_serdes;		phy->ops.read_reg = igb_read_phy_reg_gs40g;
			phy->ops.write_reg = igb_write_phy_reg_gs40g;
	break;		break;
	default:		default:
	break;		phy->ops.read_reg = igb_read_phy_reg_igp;
			phy->ops.write_reg = igb_write_phy_reg_igp;
			}
	}		}

	/* Set mta register count */		/* set lan id */
	mac->mta_reg_count = 128;		hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
	/* Set rar entry count */		E1000_STATUS_FUNC_SHIFT;
	switch (mac->type) {
	case e1000_82576:		/* Set phy->phy_addr and phy->id. */
	mac->rar_entry_count = E1000_RAR_ENTRIES_82576;		ret_val = igb_get_phy_id_82575(hw);
			if (ret_val)
			return ret_val;

			/* Verify phy id and set remaining function pointers */
			switch (phy->id) {
			case I347AT4_E_PHY_ID:
			case M88E1112_E_PHY_ID:
			case M88E1111_I_PHY_ID:
			phy->type = e1000_phy_m88;
			phy->ops.get_phy_info = igb_get_phy_info_m88;
			if (phy->id == I347AT4_E_PHY_ID \|\|
			phy->id == M88E1112_E_PHY_ID)
			phy->ops.get_cable_length =
			igb_get_cable_length_m88_gen2;
			else
			phy->ops.get_cable_length = igb_get_cable_length_m88;
			phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
	break;		break;
	case e1000_82580:		case IGP03E1000_E_PHY_ID:
	mac->rar_entry_count = E1000_RAR_ENTRIES_82580;		phy->type = e1000_phy_igp_3;
			phy->ops.get_phy_info = igb_get_phy_info_igp;
			phy->ops.get_cable_length = igb_get_cable_length_igp_2;
			phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
			phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
			phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
	break;		break;
	case e1000_i350:		case I82580_I_PHY_ID:
	mac->rar_entry_count = E1000_RAR_ENTRIES_I350;		case I350_I_PHY_ID:
			phy->type = e1000_phy_82580;
			phy->ops.force_speed_duplex =
			igb_phy_force_speed_duplex_82580;
			phy->ops.get_cable_length = igb_get_cable_length_82580;
			phy->ops.get_phy_info = igb_get_phy_info_82580;
			phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
			phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
	break;		break;
	default:		case I210_I_PHY_ID:
	mac->rar_entry_count = E1000_RAR_ENTRIES_82575;		phy->type = e1000_phy_i210;
			phy->ops.check_polarity = igb_check_polarity_m88;
			phy->ops.get_phy_info = igb_get_phy_info_m88;
			phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
			phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
			phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
			phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
	break;		break;
			default:
			ret_val = -E1000_ERR_PHY;
			goto out;
	}		}
	/* reset */
	if (mac->type >= e1000_82580)
	mac->ops.reset_hw = igb_reset_hw_82580;
	else
	mac->ops.reset_hw = igb_reset_hw_82575;

	if (mac->type >= e1000_i210) {		out:
	mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;		return ret_val;
	mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
	} else {
	mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
	mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
	}		}

	/* Set if part includes ASF firmware */		/**
	mac->asf_firmware_present = true;		* igb_init_nvm_params_82575 - Init NVM func ptrs.
	/* Set if manageability features are enabled. */		* @hw: pointer to the HW structure
	mac->arc_subsystem_valid =		**/
	(rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)		s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
	? true : false;		{
	/* enable EEE on i350 parts and later parts */		struct e1000_nvm_info *nvm = &hw->nvm;
	if (mac->type >= e1000_i350)		u32 eecd = rd32(E1000_EECD);
	dev_spec->eee_disable = false;		u16 size;
	else
	dev_spec->eee_disable = true;
	/* physical interface link setup */
	mac->ops.setup_physical_interface =
	(hw->phy.media_type == e1000_media_type_copper)
	? igb_setup_copper_link_82575
	: igb_setup_serdes_link_82575;

	/* NVM initialization */
	eecd = rd32(E1000_EECD);
	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>		size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
	E1000_EECD_SIZE_EX_SHIFT);		E1000_EECD_SIZE_EX_SHIFT);
			/* Added to a constant, "size" becomes the left-shift value
	/*
	* Added to a constant, "size" becomes the left-shift value
	* for setting word_size.		* for setting word_size.
	*/		*/
	size += NVM_WORD_SIZE_BASE_SHIFT;		size += NVM_WORD_SIZE_BASE_SHIFT;

	/*		/* Just in case size is out of range, cap it to the largest
	* Check for invalid size		* EEPROM size supported
	*/		*/
	if ((hw->mac.type == e1000_82576) && (size > 15)) {		if (size > 15)
	pr_notice("The NVM size is not valid, defaulting to 32K\n");
	size = 15;		size = 15;
	}

	nvm->word_size = 1 << size;		nvm->word_size = 1 << size;
	if (hw->mac.type < e1000_i210) {		if (hw->mac.type < e1000_i210) {
	nvm->opcode_bits = 8;		nvm->opcode_bits = 8;
	nvm->delay_usec = 1;		nvm->delay_usec = 1;

	switch (nvm->override) {		switch (nvm->override) {
	case e1000_nvm_override_spi_large:		case e1000_nvm_override_spi_large:
	nvm->page_size = 32;		nvm->page_size = 32;
	@@ -277,18 +261,18 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
	nvm->address_bits = 8;		nvm->address_bits = 8;
	break;		break;
	default:		default:
	nvm->page_size = eecd		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
	& E1000_EECD_ADDR_BITS ? 32 : 8;		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
	nvm->address_bits = eecd		16 : 8;
	& E1000_EECD_ADDR_BITS ? 16 : 8;
	break;		break;
	}		}
	if (nvm->word_size == (1 << 15))		if (nvm->word_size == (1 << 15))
	nvm->page_size = 128;		nvm->page_size = 128;

	nvm->type = e1000_nvm_eeprom_spi;		nvm->type = e1000_nvm_eeprom_spi;
	} else		} else {
	nvm->type = e1000_nvm_flash_hw;		nvm->type = e1000_nvm_flash_hw;
			}

	/* NVM Function Pointers */		/* NVM Function Pointers */
	switch (hw->mac.type) {		switch (hw->mac.type) {
	@@ -345,118 +329,176 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
	break;		break;
	}		}

	/* if part supports SR-IOV then initialize mailbox parameters */		return 0;
			}

			/**
			* igb_init_mac_params_82575 - Init MAC func ptrs.
			* @hw: pointer to the HW structure
			**/
			static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
			{
			struct e1000_mac_info *mac = &hw->mac;
			struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;

			/* Set mta register count */
			mac->mta_reg_count = 128;
			/* Set rar entry count */
	switch (mac->type) {		switch (mac->type) {
	case e1000_82576:		case e1000_82576:
			mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
			break;
			case e1000_82580:
			mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
			break;
	case e1000_i350:		case e1000_i350:
	igb_init_mbx_params_pf(hw);		mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
	break;		break;
	default:		default:
			mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
	break;		break;
	}		}
			/* reset */
			if (mac->type >= e1000_82580)
			mac->ops.reset_hw = igb_reset_hw_82580;
			else
			mac->ops.reset_hw = igb_reset_hw_82575;

	/* setup PHY parameters */		if (mac->type >= e1000_i210) {
	if (phy->media_type != e1000_media_type_copper) {		mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
	phy->type = e1000_phy_none;		mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
	return 0;
	}

	phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
	phy->reset_delay_us = 100;

	ctrl_ext = rd32(E1000_CTRL_EXT);

	/* PHY function pointers */
	if (igb_sgmii_active_82575(hw)) {
	phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
	ctrl_ext \|= E1000_CTRL_I2C_ENA;
	} else {		} else {
	phy->ops.reset = igb_phy_hw_reset;		mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
	ctrl_ext &= ~E1000_CTRL_I2C_ENA;		mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
	}		}

	wr32(E1000_CTRL_EXT, ctrl_ext);		/* Set if part includes ASF firmware */
	igb_reset_mdicnfg_82580(hw);		mac->asf_firmware_present = true;
			/* Set if manageability features are enabled. */
			mac->arc_subsystem_valid =
			(rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
			? true : false;
			/* enable EEE on i350 parts and later parts */
			if (mac->type >= e1000_i350)
			dev_spec->eee_disable = false;
			else
			dev_spec->eee_disable = true;
			/* physical interface link setup */
			mac->ops.setup_physical_interface =
			(hw->phy.media_type == e1000_media_type_copper)
			? igb_setup_copper_link_82575
			: igb_setup_serdes_link_82575;

	if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {		return 0;
	phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
	phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
	} else if ((hw->mac.type == e1000_82580)
	\|\| (hw->mac.type == e1000_i350)) {
	phy->ops.read_reg = igb_read_phy_reg_82580;
	phy->ops.write_reg = igb_write_phy_reg_82580;
	} else if (hw->phy.type >= e1000_phy_i210) {
	phy->ops.read_reg = igb_read_phy_reg_gs40g;
	phy->ops.write_reg = igb_write_phy_reg_gs40g;
	} else {
	phy->ops.read_reg = igb_read_phy_reg_igp;
	phy->ops.write_reg = igb_write_phy_reg_igp;
	}		}

	/* set lan id */		static s32 igb_get_invariants_82575(struct e1000_hw *hw)
	hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>		{
	E1000_STATUS_FUNC_SHIFT;		struct e1000_mac_info *mac = &hw->mac;
			struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
	/* Set phy->phy_addr and phy->id. */		s32 ret_val;
	ret_val = igb_get_phy_id_82575(hw);		u32 ctrl_ext = 0;
	if (ret_val)
	return ret_val;

	/* Verify phy id and set remaining function pointers */		switch (hw->device_id) {
	switch (phy->id) {		case E1000_DEV_ID_82575EB_COPPER:
	case I347AT4_E_PHY_ID:		case E1000_DEV_ID_82575EB_FIBER_SERDES:
	case M88E1112_E_PHY_ID:		case E1000_DEV_ID_82575GB_QUAD_COPPER:
	case M88E1111_I_PHY_ID:		mac->type = e1000_82575;
	phy->type = e1000_phy_m88;		break;
	phy->ops.get_phy_info = igb_get_phy_info_m88;		case E1000_DEV_ID_82576:
			case E1000_DEV_ID_82576_NS:
			case E1000_DEV_ID_82576_NS_SERDES:
			case E1000_DEV_ID_82576_FIBER:
			case E1000_DEV_ID_82576_SERDES:
			case E1000_DEV_ID_82576_QUAD_COPPER:
			case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
			case E1000_DEV_ID_82576_SERDES_QUAD:
			mac->type = e1000_82576;
			break;
			case E1000_DEV_ID_82580_COPPER:
			case E1000_DEV_ID_82580_FIBER:
			case E1000_DEV_ID_82580_QUAD_FIBER:
			case E1000_DEV_ID_82580_SERDES:
			case E1000_DEV_ID_82580_SGMII:
			case E1000_DEV_ID_82580_COPPER_DUAL:
			case E1000_DEV_ID_DH89XXCC_SGMII:
			case E1000_DEV_ID_DH89XXCC_SERDES:
			case E1000_DEV_ID_DH89XXCC_BACKPLANE:
			case E1000_DEV_ID_DH89XXCC_SFP:
			mac->type = e1000_82580;
			break;
			case E1000_DEV_ID_I350_COPPER:
			case E1000_DEV_ID_I350_FIBER:
			case E1000_DEV_ID_I350_SERDES:
			case E1000_DEV_ID_I350_SGMII:
			mac->type = e1000_i350;
			break;
			case E1000_DEV_ID_I210_COPPER:
			case E1000_DEV_ID_I210_COPPER_OEM1:
			case E1000_DEV_ID_I210_COPPER_IT:
			case E1000_DEV_ID_I210_FIBER:
			case E1000_DEV_ID_I210_SERDES:
			case E1000_DEV_ID_I210_SGMII:
			mac->type = e1000_i210;
			break;
			case E1000_DEV_ID_I211_COPPER:
			mac->type = e1000_i211;
			break;
			default:
			return -E1000_ERR_MAC_INIT;
			break;
			}

	if (phy->id == I347AT4_E_PHY_ID \|\|		/* Set media type */
	phy->id == M88E1112_E_PHY_ID)		/*
	phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;		* The 82575 uses bits 22:23 for link mode. The mode can be changed
	else		* based on the EEPROM. We cannot rely upon device ID. There
	phy->ops.get_cable_length = igb_get_cable_length_m88;		* is no distinguishable difference between fiber and internal
			* SerDes mode on the 82575. There can be an external PHY attached
			* on the SGMII interface. For this, we'll set sgmii_active to true.
			*/
			hw->phy.media_type = e1000_media_type_copper;
			dev_spec->sgmii_active = false;

	if (phy->id == I210_I_PHY_ID) {		ctrl_ext = rd32(E1000_CTRL_EXT);
	phy->ops.get_cable_length =		switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
	igb_get_cable_length_m88_gen2;		case E1000_CTRL_EXT_LINK_MODE_SGMII:
	phy->ops.set_d0_lplu_state =		dev_spec->sgmii_active = true;
	igb_set_d0_lplu_state_82580;
	phy->ops.set_d3_lplu_state =
	igb_set_d3_lplu_state_82580;
	}
	phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
	break;		break;
	case IGP03E1000_E_PHY_ID:		case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
	phy->type = e1000_phy_igp_3;		case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
	phy->ops.get_phy_info = igb_get_phy_info_igp;		hw->phy.media_type = e1000_media_type_internal_serdes;
	phy->ops.get_cable_length = igb_get_cable_length_igp_2;
	phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
	phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
	phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
	break;		break;
	case I82580_I_PHY_ID:		default:
	case I350_I_PHY_ID:
	phy->type = e1000_phy_82580;
	phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
	phy->ops.get_cable_length = igb_get_cable_length_82580;
	phy->ops.get_phy_info = igb_get_phy_info_82580;
	phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
	phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
	break;		break;
	case I210_I_PHY_ID:		}
	phy->type = e1000_phy_i210;
	phy->ops.get_phy_info = igb_get_phy_info_m88;		/* mac initialization and operations */
	phy->ops.check_polarity = igb_check_polarity_m88;		ret_val = igb_init_mac_params_82575(hw);
	phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;		if (ret_val)
	phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;		goto out;
	phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
	phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;		/* NVM initialization */
			ret_val = igb_init_nvm_params_82575(hw);
			if (ret_val)
			goto out;

			/* if part supports SR-IOV then initialize mailbox parameters */
			switch (mac->type) {
			case e1000_82576:
			case e1000_i350:
			igb_init_mbx_params_pf(hw);
	break;		break;
	default:		default:
	return -E1000_ERR_PHY;		break;
	}		}

	return 0;		/* setup PHY parameters */
			ret_val = igb_init_phy_params_82575(hw);

			out:
			return ret_val;
	}		}

	/**		/**

drivers/net/ethernet/intel/igb/igb.h

+19 −2

Original line number	Original line	Diff line number	Diff line
	@@ -139,8 +139,6 @@ struct vf_data_storage {
	#define IGB_RX_HDR_LEN IGB_RXBUFFER_256		#define IGB_RX_HDR_LEN IGB_RXBUFFER_256
	#define IGB_RX_BUFSZ IGB_RXBUFFER_2048		#define IGB_RX_BUFSZ IGB_RXBUFFER_2048

	/* How many Tx Descriptors do we need to call netif_wake_queue ? */
	#define IGB_TX_QUEUE_WAKE 16
	/* How many Rx Buffers do we bundle into one write to the hardware ? */		/* How many Rx Buffers do we bundle into one write to the hardware ? */
	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */		#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */

	@@ -169,6 +167,17 @@ enum igb_tx_flags {
	#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000		#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
	#define IGB_TX_FLAGS_VLAN_SHIFT 16		#define IGB_TX_FLAGS_VLAN_SHIFT 16

			/*
			* The largest size we can write to the descriptor is 65535. In order to
			* maintain a power of two alignment we have to limit ourselves to 32K.
			*/
			#define IGB_MAX_TXD_PWR 15
			#define IGB_MAX_DATA_PER_TXD (1 << IGB_MAX_TXD_PWR)

			/* Tx Descriptors needed, worst case */
			#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
			#define DESC_NEEDED (MAX_SKB_FRAGS + 4)

	/* wrapper around a pointer to a socket buffer,		/* wrapper around a pointer to a socket buffer,
	* so a DMA handle can be stored along with the buffer */		* so a DMA handle can be stored along with the buffer */
	struct igb_tx_buffer {		struct igb_tx_buffer {
	@@ -275,10 +284,18 @@ struct igb_q_vector {
	enum e1000_ring_flags_t {		enum e1000_ring_flags_t {
	IGB_RING_FLAG_RX_SCTP_CSUM,		IGB_RING_FLAG_RX_SCTP_CSUM,
	IGB_RING_FLAG_RX_LB_VLAN_BSWAP,		IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
			IGB_RING_FLAG_RX_BUILD_SKB_ENABLED,
	IGB_RING_FLAG_TX_CTX_IDX,		IGB_RING_FLAG_TX_CTX_IDX,
	IGB_RING_FLAG_TX_DETECT_HANG		IGB_RING_FLAG_TX_DETECT_HANG
	};		};

			#define ring_uses_build_skb(ring) \
			test_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
			#define set_ring_build_skb_enabled(ring) \
			set_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
			#define clear_ring_build_skb_enabled(ring) \
			clear_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)

	#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP \| E1000_ADVTXD_DCMD_RS)		#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP \| E1000_ADVTXD_DCMD_RS)

	#define IGB_RX_DESC(R, i) \		#define IGB_RX_DESC(R, i) \

drivers/net/ethernet/intel/igb/igb_main.c

+173 −55

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/intel/ixgbe/ixgbe_main.c

+38 −20

Original line number	Original line	Diff line number	Diff line
	@@ -4480,39 +4480,57 @@ static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
	hw->subsystem_vendor_id = pdev->subsystem_vendor;		hw->subsystem_vendor_id = pdev->subsystem_vendor;
	hw->subsystem_device_id = pdev->subsystem_device;		hw->subsystem_device_id = pdev->subsystem_device;

	/* Set capability flags */		/* Set common capability flags and settings */
	rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());		rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
	adapter->ring_feature[RING_F_RSS].limit = rss;		adapter->ring_feature[RING_F_RSS].limit = rss;
	switch (hw->mac.type) {
	case ixgbe_mac_82598EB:
	if (hw->device_id == IXGBE_DEV_ID_82598AT)
	adapter->flags \|= IXGBE_FLAG_FAN_FAIL_CAPABLE;
	adapter->max_q_vectors = MAX_Q_VECTORS_82598;
	break;
	case ixgbe_mac_X540:
	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
	if (fwsm & IXGBE_FWSM_TS_ENABLED)
	adapter->flags2 \|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
	case ixgbe_mac_82599EB:
	adapter->max_q_vectors = MAX_Q_VECTORS_82599;
	adapter->flags2 \|= IXGBE_FLAG2_RSC_CAPABLE;		adapter->flags2 \|= IXGBE_FLAG2_RSC_CAPABLE;
	adapter->flags2 \|= IXGBE_FLAG2_RSC_ENABLED;		adapter->flags2 \|= IXGBE_FLAG2_RSC_ENABLED;
	if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)		adapter->ring_feature[RING_F_FDIR].limit = IXGBE_MAX_FDIR_INDICES;
	adapter->flags2 \|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;		adapter->max_q_vectors = MAX_Q_VECTORS_82599;
	/* Flow Director hash filters enabled */
	adapter->atr_sample_rate = 20;		adapter->atr_sample_rate = 20;
	adapter->ring_feature[RING_F_FDIR].limit =
	IXGBE_MAX_FDIR_INDICES;
	adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;		adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
			#ifdef CONFIG_IXGBE_DCA
			adapter->flags \|= IXGBE_FLAG_DCA_CAPABLE;
			#endif
	#ifdef IXGBE_FCOE		#ifdef IXGBE_FCOE
	adapter->flags \|= IXGBE_FLAG_FCOE_CAPABLE;		adapter->flags \|= IXGBE_FLAG_FCOE_CAPABLE;
	adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;		adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
	#ifdef CONFIG_IXGBE_DCB		#ifdef CONFIG_IXGBE_DCB
	/* Default traffic class to use for FCoE */		/* Default traffic class to use for FCoE */
	adapter->fcoe.up = IXGBE_FCOE_DEFTC;		adapter->fcoe.up = IXGBE_FCOE_DEFTC;
	#endif		#endif /* CONFIG_IXGBE_DCB */
			#endif /* IXGBE_FCOE */

			/* Set MAC specific capability flags and exceptions */
			switch (hw->mac.type) {
			case ixgbe_mac_82598EB:
			adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
			adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;

			if (hw->device_id == IXGBE_DEV_ID_82598AT)
			adapter->flags \|= IXGBE_FLAG_FAN_FAIL_CAPABLE;

			adapter->max_q_vectors = MAX_Q_VECTORS_82598;
			adapter->ring_feature[RING_F_FDIR].limit = 0;
			adapter->atr_sample_rate = 0;
			adapter->fdir_pballoc = 0;
			#ifdef IXGBE_FCOE
			adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
			adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
			#ifdef CONFIG_IXGBE_DCB
			adapter->fcoe.up = 0;
			#endif /* IXGBE_DCB */
	#endif /* IXGBE_FCOE */		#endif /* IXGBE_FCOE */
	break;		break;
			case ixgbe_mac_82599EB:
			if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
			adapter->flags2 \|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
			break;
			case ixgbe_mac_X540:
			fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
			if (fwsm & IXGBE_FWSM_TS_ENABLED)
			adapter->flags2 \|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
			break;
	default:		default:
	break;		break;
	}		}