Merge branch 'reset' into release (f7f28f7e) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/acpi/acpica/hwxface.c

+5 −5

Original line number	Diff line number	Diff line
		@@ -80,14 +80,14 @@ acpi_status acpi_reset(void)

		if (reset_reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
		/*
		* For I/O space, write directly to the OSL. This bypasses the port
		* validation mechanism, which may block a valid write to the reset
		* register.
		* For I/O space, write directly to the OSL. This
		* bypasses the port validation mechanism, which may
		* block a valid write to the reset register. Spec
		* section 4.7.3.6 requires register width to be 8.
		*/
		status =
		acpi_os_write_port((acpi_io_address) reset_reg->address,
		acpi_gbl_FADT.reset_value,
		reset_reg->bit_width);
		acpi_gbl_FADT.reset_value, 8);
		} else {
		/* Write the reset value to the reset register */

+9 −5

Original line number	Diff line number	Diff line
		@@ -15,9 +15,15 @@ void acpi_reboot(void)

		rr = &acpi_gbl_FADT.reset_register;

		/* Is the reset register supported? */
		if (!(acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER) \|\|
		rr->bit_width != 8 \|\| rr->bit_offset != 0)
		/* ACPI reset register was only introduced with v2 of the FADT */

		if (acpi_gbl_FADT.header.revision < 2)
		return;

		/* Is the reset register supported? The spec says we should be
		* checking the bit width and bit offset, but Windows ignores
		* these fields */
		if (!(acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER))
		return;

		reset_value = acpi_gbl_FADT.reset_value;
		@@ -45,6 +51,4 @@ void acpi_reboot(void)
		acpi_reset();
		break;
		}
		/* Wait ten seconds */
		acpi_os_stall(10000000);
		}