Loading arch/arm/boot/dts/qcom/msm8937-vidc.dtsi +6 −0 Original line number Diff line number Diff line Loading @@ -37,6 +37,12 @@ <244800 308571428 0x00000004>, /* 1080p@30 720p@30 */ <97200 240000000 0x00000004>, /* FWVGA@60 */ <48600 166150000 0x00000004>; /* FWVGA@30 VGA@30 */ qcom,dcvs-tbl = <108000 10800 244800 0x00000004>, /* Encoder */ <108000 10800 244800 0x0f00000c>; /* Decoder */ qcom,dcvs-limit = <8160 30>, /* Encoder */ <8160 30>; /* Decoder */ qcom,hfi = "venus"; qcom,reg-presets = <0xe0020 0x05555556>, <0xe0024 0x05555556>, Loading arch/arm/boot/dts/qcom/msm8996-vidc.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -49,6 +49,16 @@ < 489600 150000000 0xffffffff>, /* 1080p @ 60 */ < 244800 75000000 0xffffffff>; /* 1080p @ 30 */ qcom,dcvs-tbl = <972000 972000 19944000 0x3f00000c>, /* UHD 30 */ <489600 489600 972000 0x3f00000c>, /* 1080p 60 */ <244800 244800 489600 0x3f00000c>, /* 1080p 30 */ <829440 489600 972000 0x04000004>; /* DCI 24 */ qcom,dcvs-limit = <32400 30>, /* Encoder UHD */ <14400 30>; /* Decoder WQHD */ /* Table lists <video_core_freq imem_ab> pairs. * imem_ab value determines the imem clock frequency for the * corresponding video core frequency. Loading Loading
arch/arm/boot/dts/qcom/msm8937-vidc.dtsi +6 −0 Original line number Diff line number Diff line Loading @@ -37,6 +37,12 @@ <244800 308571428 0x00000004>, /* 1080p@30 720p@30 */ <97200 240000000 0x00000004>, /* FWVGA@60 */ <48600 166150000 0x00000004>; /* FWVGA@30 VGA@30 */ qcom,dcvs-tbl = <108000 10800 244800 0x00000004>, /* Encoder */ <108000 10800 244800 0x0f00000c>; /* Decoder */ qcom,dcvs-limit = <8160 30>, /* Encoder */ <8160 30>; /* Decoder */ qcom,hfi = "venus"; qcom,reg-presets = <0xe0020 0x05555556>, <0xe0024 0x05555556>, Loading
arch/arm/boot/dts/qcom/msm8996-vidc.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -49,6 +49,16 @@ < 489600 150000000 0xffffffff>, /* 1080p @ 60 */ < 244800 75000000 0xffffffff>; /* 1080p @ 30 */ qcom,dcvs-tbl = <972000 972000 19944000 0x3f00000c>, /* UHD 30 */ <489600 489600 972000 0x3f00000c>, /* 1080p 60 */ <244800 244800 489600 0x3f00000c>, /* 1080p 30 */ <829440 489600 972000 0x04000004>; /* DCI 24 */ qcom,dcvs-limit = <32400 30>, /* Encoder UHD */ <14400 30>; /* Decoder WQHD */ /* Table lists <video_core_freq imem_ab> pairs. * imem_ab value determines the imem clock frequency for the * corresponding video core frequency. Loading