Loading arch/arm/boot/dts/qcom/msm8952-coresight.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -357,7 +357,7 @@ coresight-id = <18>; coresight-name = "coresight-csr"; coresight-nr-inports = <0>; qcom,blk-size = <1>; qcom,blk-size = <2>; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; Loading Loading @@ -781,7 +781,7 @@ hwevent: hwevent@86c000 { compatible = "qcom,coresight-hwevent"; reg = <0x86c000 0x108>, reg = <0x86c000 0x148>, <0x86cfb0 0x4>, <0x78c5010 0x4>, <0x7885010 0x4>; Loading Loading
arch/arm/boot/dts/qcom/msm8952-coresight.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -357,7 +357,7 @@ coresight-id = <18>; coresight-name = "coresight-csr"; coresight-nr-inports = <0>; qcom,blk-size = <1>; qcom,blk-size = <2>; clocks = <&clock_gcc clk_qdss_clk>, <&clock_gcc clk_qdss_a_clk>; Loading Loading @@ -781,7 +781,7 @@ hwevent: hwevent@86c000 { compatible = "qcom,coresight-hwevent"; reg = <0x86c000 0x108>, reg = <0x86c000 0x148>, <0x86cfb0 0x4>, <0x78c5010 0x4>, <0x7885010 0x4>; Loading