Loading Documentation/devicetree/bindings/regulator/gdsc-regulator.txt +2 −0 Original line number Diff line number Diff line Loading @@ -48,6 +48,8 @@ Optional properties: the api which will allow clearing the bits. - qcom,gds-timeout: Maximum time (in usecs) that might be taken by a GDSC to enable. - qcom,reset-aon-logic: If present, the GPU DEMET cells need to be reset while enabling the GX GDSC. Example: gdsc_oxili_gx: qcom,gdsc@fd8c4024 { Loading arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -143,6 +143,7 @@ <0x5066090 0x4>; reg-names = "base", "domain_addr", "sw_reset"; qcom,retain-periph; qcom,reset-aon-logic; status = "disabled"; }; }; drivers/clk/msm/gdsc.c +25 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,7 @@ #define HW_CONTROL_MASK BIT(1) #define SW_COLLAPSE_MASK BIT(0) #define GMEM_CLAMP_IO_MASK BIT(0) #define GMEM_RESET_MASK BIT(4) #define BCR_BLK_ARES_BIT BIT(0) /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ Loading @@ -58,6 +59,7 @@ struct gdsc { bool no_status_check_on_disable; bool is_gdsc_enabled; bool allow_clear; bool reset_aon; void __iomem *domain_addr; void __iomem *hw_ctrl_addr; void __iomem *sw_reset_addr; Loading Loading @@ -167,6 +169,26 @@ static int gdsc_enable(struct regulator_dev *rdev) } if (sc->domain_addr) { if (sc->reset_aon) { regval = readl_relaxed(sc->domain_addr); regval |= GMEM_RESET_MASK; writel_relaxed(regval, sc->domain_addr); /* * Keep reset asserted for at-least 1us before * continuing. */ wmb(); udelay(1); regval &= ~GMEM_RESET_MASK; writel_relaxed(regval, sc->domain_addr); /* * Make sure GMEM_RESET is de-asserted before * continuing. */ wmb(); } regval = readl_relaxed(sc->domain_addr); regval &= ~GMEM_CLAMP_IO_MASK; writel_relaxed(regval, sc->domain_addr); Loading Loading @@ -469,6 +491,9 @@ static int gdsc_probe(struct platform_device *pdev) return -ENOMEM; } sc->reset_aon = of_property_read_bool(pdev->dev.of_node, "qcom,reset-aon-logic"); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sw_reset"); if (res) { Loading Loading
Documentation/devicetree/bindings/regulator/gdsc-regulator.txt +2 −0 Original line number Diff line number Diff line Loading @@ -48,6 +48,8 @@ Optional properties: the api which will allow clearing the bits. - qcom,gds-timeout: Maximum time (in usecs) that might be taken by a GDSC to enable. - qcom,reset-aon-logic: If present, the GPU DEMET cells need to be reset while enabling the GX GDSC. Example: gdsc_oxili_gx: qcom,gdsc@fd8c4024 { Loading
arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -143,6 +143,7 @@ <0x5066090 0x4>; reg-names = "base", "domain_addr", "sw_reset"; qcom,retain-periph; qcom,reset-aon-logic; status = "disabled"; }; };
drivers/clk/msm/gdsc.c +25 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,7 @@ #define HW_CONTROL_MASK BIT(1) #define SW_COLLAPSE_MASK BIT(0) #define GMEM_CLAMP_IO_MASK BIT(0) #define GMEM_RESET_MASK BIT(4) #define BCR_BLK_ARES_BIT BIT(0) /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ Loading @@ -58,6 +59,7 @@ struct gdsc { bool no_status_check_on_disable; bool is_gdsc_enabled; bool allow_clear; bool reset_aon; void __iomem *domain_addr; void __iomem *hw_ctrl_addr; void __iomem *sw_reset_addr; Loading Loading @@ -167,6 +169,26 @@ static int gdsc_enable(struct regulator_dev *rdev) } if (sc->domain_addr) { if (sc->reset_aon) { regval = readl_relaxed(sc->domain_addr); regval |= GMEM_RESET_MASK; writel_relaxed(regval, sc->domain_addr); /* * Keep reset asserted for at-least 1us before * continuing. */ wmb(); udelay(1); regval &= ~GMEM_RESET_MASK; writel_relaxed(regval, sc->domain_addr); /* * Make sure GMEM_RESET is de-asserted before * continuing. */ wmb(); } regval = readl_relaxed(sc->domain_addr); regval &= ~GMEM_CLAMP_IO_MASK; writel_relaxed(regval, sc->domain_addr); Loading Loading @@ -469,6 +491,9 @@ static int gdsc_probe(struct platform_device *pdev) return -ENOMEM; } sc->reset_aon = of_property_read_bool(pdev->dev.of_node, "qcom,reset-aon-logic"); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sw_reset"); if (res) { Loading