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Commit f68bfdb1 authored by Jacob Keller's avatar Jacob Keller Committed by Jeff Kirsher
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ixgbe: check Core Clock Disable bit



This patch corrects the stop_mac_link_on_d3 function in ixgbe_82599 by
checking the Core Clock Disable bit before stopping link.

CC: Arun Sharma <asharma@fb.com>
Reported-by: default avatarChris Pavlas <chris.pavlas@intel.com>
Signed-off-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent f8cf7a00
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+5 −1
Original line number Diff line number Diff line
@@ -518,8 +518,12 @@ out:
static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
{
	u32 autoc2_reg;
	u16 ee_ctrl_2 = 0;

	if (!hw->mng_fw_enabled && !hw->wol_enabled) {
	hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);

	if (!hw->mng_fw_enabled && !hw->wol_enabled &&
	    ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
		autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
		autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
		IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
+3 −0
Original line number Diff line number Diff line
@@ -1793,6 +1793,9 @@ enum {
#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */
#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */

#define IXGBE_EEPROM_CTRL_2	1 /* EEPROM CTRL word 2 */
#define IXGBE_EEPROM_CCD_BIT	2 /* EEPROM Core Clock Disable bit */

#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
#endif