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Commit f5bfb681 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "arm64: issue isb when trapping CNTVCT_EL0 access"

parents 7322d91d 1ad7cba0

arch/arm64/include/asm/esr.h

+40 −0
Original line number Diff line number Diff line
@@ -134,6 +134,46 @@ 
#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)

#define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)



/* ISS field definitions for System instruction traps */

#define ESR_ELx_SYS64_ISS_RES0_SHIFT	22

#define ESR_ELx_SYS64_ISS_RES0_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)

#define ESR_ELx_SYS64_ISS_DIR_MASK	0x1

#define ESR_ELx_SYS64_ISS_DIR_READ	0x1

#define ESR_ELx_SYS64_ISS_DIR_WRITE	0x0



#define ESR_ELx_SYS64_ISS_RT_SHIFT	5

#define ESR_ELx_SYS64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)

#define ESR_ELx_SYS64_ISS_CRM_SHIFT	1

#define ESR_ELx_SYS64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)

#define ESR_ELx_SYS64_ISS_CRN_SHIFT	10

#define ESR_ELx_SYS64_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)

#define ESR_ELx_SYS64_ISS_OP1_SHIFT	14

#define ESR_ELx_SYS64_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)

#define ESR_ELx_SYS64_ISS_OP2_SHIFT	17

#define ESR_ELx_SYS64_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)

#define ESR_ELx_SYS64_ISS_OP0_SHIFT	20

#define ESR_ELx_SYS64_ISS_OP0_MASK	(UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)

#define ESR_ELx_SYS64_ISS_SYS_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \

					 ESR_ELx_SYS64_ISS_OP1_MASK | \

					 ESR_ELx_SYS64_ISS_OP2_MASK | \

					 ESR_ELx_SYS64_ISS_CRN_MASK | \

					 ESR_ELx_SYS64_ISS_CRM_MASK)

#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \

					(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \

					 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \

					 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \

					 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \

					 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))



#define ESR_ELx_SYS64_ISS_SYS_OP_MASK	(ESR_ELx_SYS64_ISS_SYS_MASK | \

					 ESR_ELx_SYS64_ISS_DIR_MASK)



#define ESR_ELx_SYS64_ISS_SYS_CNTVCT	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \

					 ESR_ELx_SYS64_ISS_DIR_READ)



#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ	(ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \

					 ESR_ELx_SYS64_ISS_DIR_READ)



#ifndef __ASSEMBLY__

#include <asm/types.h>

arch/arm64/kernel/entry.S

+11 −1
Original line number Diff line number Diff line
@@ -484,7 +484,7 @@ el0_sync: 
	cmp	x24, #ESR_ELx_EC_FP_EXC64	// FP/ASIMD exception

	b.eq	el0_fpsimd_exc

	cmp	x24, #ESR_ELx_EC_SYS64		// configurable trap

	b.eq	el0_undef

	b.eq	el0_sys

	cmp	x24, #ESR_ELx_EC_SP_ALIGN	// stack alignment exception

	b.eq	el0_sp_pc

	cmp	x24, #ESR_ELx_EC_PC_ALIGN	// pc alignment exception
@@ -621,6 +621,16 @@ el0_undef: 
	mov	x0, sp

	bl	do_undefinstr

	b	ret_to_user

el0_sys:

	/*

	 * System instructions, for trapped cache maintenance instructions

	 */

	enable_dbg_and_irq

	ct_user_exit

	mov	x0, x25

	mov	x1, sp

	bl	do_sysinstr

	b	ret_to_user

el0_dbg:

	/*

	 * Debug exception handling

arch/arm64/kernel/traps.c

+33 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#include <linux/syscalls.h>



#include <asm/atomic.h>

#include <asm/barrier.h>

#include <asm/debug-monitors.h>

#include <asm/esr.h>

#include <asm/traps.h>
@@ -399,6 +400,38 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) 
	arm64_notify_die("Oops - undefined instruction", regs, &info, 0);

}



static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)

{

	int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;



	isb();

	if (rt != 31)

		regs->regs[rt] = arch_counter_get_cntvct();

	regs->pc += 4;

}



static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)

{

	int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;



	if (rt != 31)

		regs->regs[rt] = read_sysreg(cntfrq_el0);

	regs->pc += 4;

}



asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs)

{

	if ((esr & ESR_ELx_SYS64_ISS_SYS_OP_MASK) == ESR_ELx_SYS64_ISS_SYS_CNTVCT) {

		cntvct_read_handler(esr, regs);

		return;

	} else if ((esr & ESR_ELx_SYS64_ISS_SYS_OP_MASK) == ESR_ELx_SYS64_ISS_SYS_CNTFRQ) {

		cntfrq_read_handler(esr, regs);

		return;

	}



	do_undefinstr(regs);

}



long compat_arm_syscall(struct pt_regs *regs);



asmlinkage long do_ni_syscall(struct pt_regs *regs)