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Commit f5868f05 authored by Paul Bolle's avatar Paul Bolle Committed by Ralf Baechle
Browse files

MIPS: Replace CONFIG_MIPS64 and CONFIG_MIPS32_R2 



Commit 597ce172 ("MIPS: Support for 64-bit FP with O32 binaries")
introduced references to two undefined Kconfig macros. CONFIG_MIPS32_R2
should clearly be replaced with CONFIG_CPU_MIPS32_R2. And CONFIG_MIPS64
should be replaced with CONFIG_64BIT.

Signed-off-by: default avatarPaul Bolle <pebolle@tiscali.nl>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/6522/


Tested-by: default avatarAaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 51061b88

arch/mips/include/asm/asmmacro.h

+2 −2
Original line number Diff line number Diff line
@@ -106,7 +106,7 @@ 
	.endm



	.macro	fpu_save_double thread status tmp

#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)

	sll	\tmp, \status, 5

	bgez	\tmp, 10f

	fpu_save_16odd \thread
@@ -159,7 +159,7 @@ 
	.endm



	.macro	fpu_restore_double thread status tmp

#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)

	sll	\tmp, \status, 5

	bgez	\tmp, 10f				# 16 register mode?

arch/mips/include/asm/fpu.h

+1 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ static inline int __enable_fpu(enum fpu_mode mode) 
		return 0;



	case FPU_64BIT:

#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_MIPS64))

#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT))

		/* we only have a 32-bit FPU */

		return SIGFPE;

#endif

arch/mips/kernel/r4k_fpu.S

+4 −4
Original line number Diff line number Diff line
@@ -35,9 +35,9 @@ 
LEAF(_save_fp_context)

	cfc1	t1, fcr31



#if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2)

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)

	.set	push

#ifdef CONFIG_MIPS32_R2

#ifdef CONFIG_CPU_MIPS32_R2

	.set	mips64r2

	mfc0	t0, CP0_STATUS

	sll	t0, t0, 5
@@ -148,9 +148,9 @@ LEAF(_save_fp_context32) 
LEAF(_restore_fp_context)

	EX	lw t0, SC_FPC_CSR(a0)



#if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2)

#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)

	.set	push

#ifdef CONFIG_MIPS32_R2

#ifdef CONFIG_CPU_MIPS32_R2

	.set	mips64r2

	mfc0	t0, CP0_STATUS

	sll	t0, t0, 5