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Commit f5430f93 authored by Jeremy Fitzhardinge's avatar Jeremy Fitzhardinge Committed by Ingo Molnar
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x86: update reference for PAE tlb flushing 



Remove bogus reference to "Pentium-II erratum A13" and point to the
actual canonical source of information about what requirements x86
processors have for PAE pagetable updates.

Signed-off-by: default avatarJeremy Fitzhardinge <jeremy@xensource.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent edd6bcd8

include/asm-x86/pgalloc_32.h

+4 −2
Original line number Diff line number Diff line
@@ -80,8 +80,10 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd) 
	set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT));



	/*

	 * Pentium-II erratum A13: in PAE mode we explicitly have to flush

	 * the TLB via cr3 if the top-level pgd is changed...

	 * According to Intel App note "TLBs, Paging-Structure Caches,

	 * and Their Invalidation", April 2007, document 317080-001,

	 * section 8.1: in PAE mode we explicitly have to flush the

	 * TLB via cr3 if the top-level pgd is changed...

	 */

	if (mm == current->active_mm)

		write_cr3(read_cr3());

include/asm-x86/pgtable-3level.h

+4 −2
Original line number Diff line number Diff line
@@ -98,8 +98,10 @@ static inline void pud_clear(pud_t *pudp) 
	set_pud(pudp, __pud(0));



	/*

	 * Pentium-II erratum A13: in PAE mode we explicitly have to flush

	 * the TLB via cr3 if the top-level pgd is changed...

	 * According to Intel App note "TLBs, Paging-Structure Caches,

	 * and Their Invalidation", April 2007, document 317080-001,

	 * section 8.1: in PAE mode we explicitly have to flush the

	 * TLB via cr3 if the top-level pgd is changed...

	 *

	 * Make sure the pud entry we're updating is within the

	 * current pgd to avoid unnecessary TLB flushes.