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Commit f4ed9d9d authored by Marek Szyprowski's avatar Marek Szyprowski Committed by Greg Kroah-Hartman
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drm/exynos: gsc: Fix support for NV16/61, YUV420/YVU420 and YUV422 modes 



[ Upstream commit dd209ef809080ced903e7747ee3ef640c923a1d2 ]

Fix following issues related to planar YUV pixel format configuration:
- NV16/61 modes were incorrectly programmed as NV12/21,
- YVU420 was programmed as YUV420 on source,
- YVU420 and YUV422 were programmed as YUV420 on output.

Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: default avatarInki Dae <inki.dae@samsung.com>
Signed-off-by: default avatarSasha Levin <alexander.levin@microsoft.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 0d8e0d1c

drivers/gpu/drm/exynos/exynos_drm_gsc.c

+20 −9
Original line number Diff line number Diff line
@@ -526,21 +526,25 @@ static int gsc_src_set_fmt(struct device *dev, u32 fmt) 
			GSC_IN_CHROMA_ORDER_CRCB);

		break;

	case DRM_FORMAT_NV21:

		cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_2P);

		break;

	case DRM_FORMAT_NV61:

		cfg |= (GSC_IN_CHROMA_ORDER_CRCB |

			GSC_IN_YUV420_2P);

		cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV422_2P);

		break;

	case DRM_FORMAT_YUV422:

		cfg |= GSC_IN_YUV422_3P;

		break;

	case DRM_FORMAT_YUV420:

		cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P);

		break;

	case DRM_FORMAT_YVU420:

		cfg |= GSC_IN_YUV420_3P;

		cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_3P);

		break;

	case DRM_FORMAT_NV12:

		cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_2P);

		break;

	case DRM_FORMAT_NV16:

		cfg |= (GSC_IN_CHROMA_ORDER_CBCR |

			GSC_IN_YUV420_2P);

		cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV422_2P);

		break;

	case DRM_FORMAT_NV12MT:

		cfg |= (GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE);
@@ -796,18 +800,25 @@ static int gsc_dst_set_fmt(struct device *dev, u32 fmt) 
			GSC_OUT_CHROMA_ORDER_CRCB);

		break;

	case DRM_FORMAT_NV21:

	case DRM_FORMAT_NV61:

		cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);

		break;

	case DRM_FORMAT_NV61:

		cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV422_2P);

		break;

	case DRM_FORMAT_YUV422:

		cfg |= GSC_OUT_YUV422_3P;

		break;

	case DRM_FORMAT_YUV420:

		cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P);

		break;

	case DRM_FORMAT_YVU420:

		cfg |= GSC_OUT_YUV420_3P;

		cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_3P);

		break;

	case DRM_FORMAT_NV12:

		cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_2P);

		break;

	case DRM_FORMAT_NV16:

		cfg |= (GSC_OUT_CHROMA_ORDER_CBCR |

			GSC_OUT_YUV420_2P);

		cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV422_2P);

		break;

	case DRM_FORMAT_NV12MT:

		cfg |= (GSC_OUT_TILE_C_16x8 | GSC_OUT_TILE_MODE);

drivers/gpu/drm/exynos/regs-gsc.h

+1 −0
Original line number Diff line number Diff line
@@ -138,6 +138,7 @@ 
#define GSC_OUT_YUV420_3P		(3 << 4)

#define GSC_OUT_YUV422_1P		(4 << 4)

#define GSC_OUT_YUV422_2P		(5 << 4)

#define GSC_OUT_YUV422_3P		(6 << 4)

#define GSC_OUT_YUV444			(7 << 4)

#define GSC_OUT_TILE_TYPE_MASK		(1 << 2)

#define GSC_OUT_TILE_C_16x8		(0 << 2)