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Commit f467e4bf authored by Hillf Danton's avatar Hillf Danton Committed by Ralf Baechle
Browse files

MIPS: Flush huge TLB 



When flushing TLB, if @vma is backed by huge page, we could flush huge
TLB, due to that huge page is defined to be far from normal page.

Signed-off-by: default avatarHillf Danton <dhillf@gmail.com>
Acked-by: default avatarDavid Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: "Jayachandran C." <jayachandranc@netlogicmicro.com>
Patchwork: https://patchwork.linux-mips.org/patch/2825/


Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
Acked-by: default avatarHillf Danton <dhillf@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/3114/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 8b5690f8

arch/mips/include/asm/page.h

+8 −0
Original line number Diff line number Diff line
@@ -38,6 +38,14 @@ 
#define HPAGE_SIZE	(_AC(1,UL) << HPAGE_SHIFT)

#define HPAGE_MASK	(~(HPAGE_SIZE - 1))

#define HUGETLB_PAGE_ORDER	(HPAGE_SHIFT - PAGE_SHIFT)

#else /* !CONFIG_HUGETLB_PAGE */

# ifndef BUILD_BUG

#  define BUILD_BUG() do { extern void __build_bug(void); __build_bug(); } while (0)

# endif

#define HPAGE_SHIFT	({BUILD_BUG(); 0; })

#define HPAGE_SIZE	({BUILD_BUG(); 0; })

#define HPAGE_MASK	({BUILD_BUG(); 0; })

#define HUGETLB_PAGE_ORDER	({BUILD_BUG(); 0; })

#endif /* CONFIG_HUGETLB_PAGE */



#ifndef __ASSEMBLY__

arch/mips/mm/tlb-r4k.c

+14 −6
Original line number Diff line number Diff line
@@ -120,21 +120,29 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 


	if (cpu_context(cpu, mm) != 0) {

		unsigned long size, flags;

		int huge = is_vm_hugetlb_page(vma);



		ENTER_CRITICAL(flags);

		size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;

		size = (size + 1) >> 1;

		if (huge) {

			start = round_down(start, HPAGE_SIZE);

			end = round_up(end, HPAGE_SIZE);

			size = (end - start) >> HPAGE_SHIFT;

		} else {

			start = round_down(start, PAGE_SIZE << 1);

			end = round_up(end, PAGE_SIZE << 1);

			size = (end - start) >> (PAGE_SHIFT + 1);

		}

		if (size <= current_cpu_data.tlbsize/2) {

			int oldpid = read_c0_entryhi();

			int newpid = cpu_asid(cpu, mm);



			start &= (PAGE_MASK << 1);

			end += ((PAGE_SIZE << 1) - 1);

			end &= (PAGE_MASK << 1);

			while (start < end) {

				int idx;



				write_c0_entryhi(start | newpid);

				if (huge)

					start += HPAGE_SIZE;

				else

					start += (PAGE_SIZE << 1);

				mtc0_tlbw_hazard();

				tlb_probe();