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Commit f4618924 authored by Amir Levy's avatar Amir Levy Committed by Gerrit - the friendly Code Review server
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msm: ipa3: Update SSR clean routine to IPAv3 FnR changes



During SSR, ipa3_q6_clean_q6_tables() AP routine is being called
to clear the Q6 filtering and routing tables at IPA core.
Due to changes to FnR at IPAv3 (Hashable and Non-Hashable tables),
the routine is updated to clear both of them.

Change-Id: Ie430c0ab9fc23128b0b277b6cab70398b2c2ebde
Signed-off-by: default avatarGhanim Fodi <gfodi@codeaurora.org>
Signed-off-by: default avatarAmir Levy <alevy@codeaurora.org>
parent 48b41f0a
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+100 −19
Original line number Diff line number Diff line
@@ -1331,15 +1331,18 @@ static u32 ipa3_get_max_flt_rt_cmds(u32 num_pipes)
{
	u32 max_cmds = 0;

	/* As many filter tables as there are pipes, x2 for IPv4 and IPv6 */
	max_cmds += num_pipes * 2;
	/*
	 * As many filter tables as there are filtering pipes,
	 *	x4 for IPv4/IPv6 and hashable/non-hashable combinations
	 */
	max_cmds += ipa3_ctx->ep_flt_num * 4;

	/* For each of the Modem routing tables */
	max_cmds += (IPA_MEM_PART(v4_modem_rt_index_hi) -
		     IPA_MEM_PART(v4_modem_rt_index_lo) + 1);
	/* For each of the Modem routing tables - x2 for hash/non-hash */
	max_cmds += ((IPA_MEM_PART(v4_modem_rt_index_hi) -
		     IPA_MEM_PART(v4_modem_rt_index_lo) + 1) * 2);

	max_cmds += (IPA_MEM_PART(v6_modem_rt_index_hi) -
		     IPA_MEM_PART(v6_modem_rt_index_lo) + 1);
	max_cmds += ((IPA_MEM_PART(v6_modem_rt_index_hi) -
		     IPA_MEM_PART(v6_modem_rt_index_lo) + 1) * 2);

	return max_cmds;
}
@@ -1353,17 +1356,18 @@ static int ipa3_q6_clean_q6_tables(void)
	int index;
	int retval;
	struct ipa3_mem_buffer mem = { 0 };
	u32 *entry;
	u64 *entry;
	u32 max_cmds = ipa3_get_max_flt_rt_cmds(ipa3_ctx->ipa_num_pipes);
	int flt_idx = 0;

	mem.base = dma_alloc_coherent(ipa3_ctx->pdev, 4, &mem.phys_base,
		GFP_KERNEL);
	mem.size = IPA_HW_TBL_HDR_WIDTH;
	mem.base = dma_alloc_coherent(ipa3_ctx->pdev, mem.size,
		&mem.phys_base, GFP_KERNEL);
	if (!mem.base) {
		IPAERR("failed to alloc DMA buff of size %d\n", mem.size);
		return -ENOMEM;
	}

	mem.size = 4;
	entry = mem.base;
	*entry = ipa3_ctx->empty_rt_tbl_mem.phys_base;

@@ -1383,15 +1387,56 @@ static int ipa3_q6_clean_q6_tables(void)
	}

	/*
	 * Iterating over all the pipes which are either invalid but connected
	 * or connected but not configured by AP.
	 * Iterating over all the filtering pipes which are
	 * either invalid but connected or connected but not configured by AP.
	 */
	for (pipe_idx = 0; pipe_idx < ipa3_ctx->ipa_num_pipes; pipe_idx++) {
		if (!ipa_is_ep_support_flt(pipe_idx))
			continue;

		if (!ipa3_ctx->ep[pipe_idx].valid ||
		    ipa3_ctx->ep[pipe_idx].skip_ep_cfg) {
			/*
			 * Need to point v4 and v6 fltr tables to an empty
			 * table
			 * Need to point v4 and v6 hash fltr tables to an
			 * empty table
			 */
			cmd[num_cmds].skip_pipeline_clear = 0;
			cmd[num_cmds].pipeline_clear_options =
				IPA_FULL_PIPELINE_CLEAR;
			cmd[num_cmds].size = mem.size;
			cmd[num_cmds].system_addr = mem.phys_base;
			cmd[num_cmds].local_addr =
				ipa3_ctx->smem_restricted_bytes +
				IPA_MEM_PART(v4_flt_hash_ofst) +
				IPA_HW_TBL_HDR_WIDTH +
				flt_idx * IPA_HW_TBL_HDR_WIDTH;

			desc[num_cmds].opcode = IPA_DMA_SHARED_MEM;
			desc[num_cmds].pyld = &cmd[num_cmds];
			desc[num_cmds].len = sizeof(*cmd);
			desc[num_cmds].type = IPA_IMM_CMD_DESC;
			num_cmds++;

			cmd[num_cmds].skip_pipeline_clear = 0;
			cmd[num_cmds].pipeline_clear_options =
				IPA_FULL_PIPELINE_CLEAR;
			cmd[num_cmds].size = mem.size;
			cmd[num_cmds].system_addr =  mem.phys_base;
			cmd[num_cmds].local_addr =
				ipa3_ctx->smem_restricted_bytes +
				IPA_MEM_PART(v6_flt_hash_ofst) +
				IPA_HW_TBL_HDR_WIDTH +
				flt_idx * IPA_HW_TBL_HDR_WIDTH;

			desc[num_cmds].opcode = IPA_DMA_SHARED_MEM;
			desc[num_cmds].pyld = &cmd[num_cmds];
			desc[num_cmds].len = sizeof(*cmd);
			desc[num_cmds].type = IPA_IMM_CMD_DESC;
			num_cmds++;

			/*
			 * Need to point v4 and v6 non-hash fltr tables to an
			 * empty table
			 */
			cmd[num_cmds].skip_pipeline_clear = 0;
			cmd[num_cmds].pipeline_clear_options =
@@ -1401,7 +1446,8 @@ static int ipa3_q6_clean_q6_tables(void)
			cmd[num_cmds].local_addr =
				ipa3_ctx->smem_restricted_bytes +
				IPA_MEM_PART(v4_flt_nhash_ofst) +
				8 + pipe_idx * 4;
				IPA_HW_TBL_HDR_WIDTH +
				flt_idx * IPA_HW_TBL_HDR_WIDTH;

			desc[num_cmds].opcode = IPA_DMA_SHARED_MEM;
			desc[num_cmds].pyld = &cmd[num_cmds];
@@ -1417,7 +1463,8 @@ static int ipa3_q6_clean_q6_tables(void)
			cmd[num_cmds].local_addr =
				ipa3_ctx->smem_restricted_bytes +
				IPA_MEM_PART(v6_flt_nhash_ofst) +
				8 + pipe_idx * 4;
				IPA_HW_TBL_HDR_WIDTH +
				flt_idx * IPA_HW_TBL_HDR_WIDTH;

			desc[num_cmds].opcode = IPA_DMA_SHARED_MEM;
			desc[num_cmds].pyld = &cmd[num_cmds];
@@ -1425,6 +1472,8 @@ static int ipa3_q6_clean_q6_tables(void)
			desc[num_cmds].type = IPA_IMM_CMD_DESC;
			num_cmds++;
		}

		flt_idx++;
	}

	/* Need to point v4/v6 modem routing tables to an empty table */
@@ -1437,7 +1486,23 @@ static int ipa3_q6_clean_q6_tables(void)
		cmd[num_cmds].size = mem.size;
		cmd[num_cmds].system_addr =  mem.phys_base;
		cmd[num_cmds].local_addr = ipa3_ctx->smem_restricted_bytes +
			IPA_MEM_PART(v4_rt_nhash_ofst) + index * 4;
			IPA_MEM_PART(v4_rt_hash_ofst) +
			index * IPA_HW_TBL_HDR_WIDTH;

		desc[num_cmds].opcode = IPA_DMA_SHARED_MEM;
		desc[num_cmds].pyld = &cmd[num_cmds];
		desc[num_cmds].len = sizeof(*cmd);
		desc[num_cmds].type = IPA_IMM_CMD_DESC;
		num_cmds++;

		cmd[num_cmds].skip_pipeline_clear = 0;
		cmd[num_cmds].pipeline_clear_options =
			IPA_FULL_PIPELINE_CLEAR;
		cmd[num_cmds].size = mem.size;
		cmd[num_cmds].system_addr =  mem.phys_base;
		cmd[num_cmds].local_addr = ipa3_ctx->smem_restricted_bytes +
			IPA_MEM_PART(v4_rt_nhash_ofst) +
			index * IPA_HW_TBL_HDR_WIDTH;

		desc[num_cmds].opcode = IPA_DMA_SHARED_MEM;
		desc[num_cmds].pyld = &cmd[num_cmds];
@@ -1455,7 +1520,23 @@ static int ipa3_q6_clean_q6_tables(void)
		cmd[num_cmds].size = mem.size;
		cmd[num_cmds].system_addr =  mem.phys_base;
		cmd[num_cmds].local_addr = ipa3_ctx->smem_restricted_bytes +
			IPA_MEM_PART(v6_rt_nhash_ofst) + index * 4;
			IPA_MEM_PART(v6_rt_hash_ofst) +
			index * IPA_HW_TBL_HDR_WIDTH;

		desc[num_cmds].opcode = IPA_DMA_SHARED_MEM;
		desc[num_cmds].pyld = &cmd[num_cmds];
		desc[num_cmds].len = sizeof(*cmd);
		desc[num_cmds].type = IPA_IMM_CMD_DESC;
		num_cmds++;

		cmd[num_cmds].skip_pipeline_clear = 0;
		cmd[num_cmds].pipeline_clear_options =
			IPA_FULL_PIPELINE_CLEAR;
		cmd[num_cmds].size = mem.size;
		cmd[num_cmds].system_addr =  mem.phys_base;
		cmd[num_cmds].local_addr = ipa3_ctx->smem_restricted_bytes +
			IPA_MEM_PART(v6_rt_nhash_ofst) +
			index * IPA_HW_TBL_HDR_WIDTH;

		desc[num_cmds].opcode = IPA_DMA_SHARED_MEM;
		desc[num_cmds].pyld = &cmd[num_cmds];