Commit f4251f3c authored Jun 26, 2016 by Tanya Finkel

ARM: dts: msm: Configure BLSP1 and BLSP12 as SPI for SBC8096



Configure BLSP1 and BLSP12 as SPI0 and SPI12 accordingly.
SPI0 and SPI12 are wired to the EEPROMs on the SBC8096 platform.

Change-Id: Iaf584cc6045f589471f0ef54088973b80d412475
Signed-off-by: Anna Hanna Sedlak Grinbaum <asedla@codeaurora.org>
Signed-off-by: Tanya Finkel <tfinkel@codeaurora.org>

parent 450bd44d

arch/arm/boot/dts/qcom/apq8096-sbc.dtsi

+12 −0

Original line number	Diff line number	Diff line
		@@ -799,6 +799,18 @@
		status = "ok";
		};

		&spi_0 {
		status = "ok";
		};

		&i2c_12 {
		status = "disabled";
		};

		&spi_12 {
		status = "ok";
		};

		&slim_msm {
		tasha_codec {
		qcom,cdc-micbias1-ext-cap;