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Commit f3ff6432 authored by Greg Ungerer's avatar Greg Ungerer
Browse files

m68k: fix ColdFire clear cache operation 



The code for clearing (invalidating) the ColdFire cache is actually performing
a push operation. Add functions to clear the cache, and fix cache_clear() to
call the appropriate clear cache function.

Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
parent b60f187f

arch/m68k/include/asm/cacheflush_mm.h

+41 −0
Original line number Diff line number Diff line
@@ -16,7 +16,48 @@ 
#define DCACHE_MAX_ADDR	0

#define DCACHE_SETMASK	0

#endif

#ifndef CACHE_MODE

#define	CACHE_MODE	0

#define	CACR_ICINVA	0

#define	CACR_DCINVA	0

#define	CACR_BCINVA	0

#endif



/*

 * ColdFire architecture has no way to clear individual cache lines, so we

 * are stuck invalidating all the cache entries when we want a clear operation.

 */

static inline void clear_cf_icache(unsigned long start, unsigned long end)

{

	__asm__ __volatile__ (

		"movec	%0,%%cacr\n\t"

		"nop"

		:

		: "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA));

}



static inline void clear_cf_dcache(unsigned long start, unsigned long end)

{

	__asm__ __volatile__ (

		"movec	%0,%%cacr\n\t"

		"nop"

		:

		: "r" (CACHE_MODE | CACR_DCINVA));

}



static inline void clear_cf_bcache(unsigned long start, unsigned long end)

{

	__asm__ __volatile__ (

		"movec	%0,%%cacr\n\t"

		"nop"

		:

		: "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA | CACR_DCINVA));

}



/*

 * Use the ColdFire cpushl instruction to push (and invalidate) cache lines.

 * The start and end addresses are cache line numbers not memory addresses.

 */

static inline void flush_cf_icache(unsigned long start, unsigned long end)

{

	unsigned long set;

arch/m68k/mm/memory.c

+1 −1
Original line number Diff line number Diff line
@@ -203,7 +203,7 @@ static inline void pushcl040(unsigned long paddr) 
void cache_clear (unsigned long paddr, int len)

{

    if (CPU_IS_COLDFIRE) {

	flush_cf_bcache(0, DCACHE_MAX_ADDR);

	clear_cf_bcache(0, DCACHE_MAX_ADDR);

    } else if (CPU_IS_040_OR_060) {

	int tmp;