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Commit f2d6e550 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-soc2-for-v3.12' of... 

Merge tag 'renesas-soc2-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

From Simon Horman:
Second Round of Renesas ARM based SoC updates for v3.12

* Increased clock coverage for r8a7740 and r8a7790 SoCs

* tag 'renesas-soc2-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

:
  ARM: shmobile: r8a7740: Add TPU clock entry for DT platforms
  ARM: shmobile: r8a7790: clocks for Ether support
  ARM: shmobile: r8a7740: Fix TPU clock name
  ARM: shmobile: Insert align directives before 4 bytes data
  ARM: shmobile: Force ARM mode to compile reset vector for secondary CPUs
  ARM: shmobile: fix compile error when CONFIG_THUMB2_KERNEL=y
  ARM: shmobile: Update romImage to relocate appended DTB

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents fc5d4622 d687f4d1

arch/arm/boot/compressed/head-shmobile.S

+39 −4
Original line number Diff line number Diff line
@@ -55,12 +55,47 @@ __tmp_stack: 
__continue:

#endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */



	/* Set board ID necessary for boot */

	ldr	r7, 1f				@ Set machine type register

	mov	r8, #0				@ pass null pointer as atag

	adr	r0, dtb_info

	ldmia	r0, {r1, r3, r4, r5, r7}



	sub	r0, r0, r1		@ calculate the delta offset

	add	r5, r5, r0		@ _edata



	ldr	lr, [r5, #0]		@ check if valid DTB is present

	cmp	lr, r3

	bne	0f



	add	r9, r7, #31		@ rounded up to a multiple

	bic	r9, r9, #31		@ ... of 32 bytes



	add	r6, r9, r5		@ copy from _edata

	add	r9, r9, r4		@ to MEMORY_START



1:	ldmdb	r6!, {r0 - r3, r10 - r12, lr}

	cmp	r6, r5

	stmdb	r9!, {r0 - r3, r10 - r12, lr}

	bhi	1b



	/* Success: Zero board ID, pointer to start of memory for atag/dtb */

	mov	r7, #0

	mov	r8, r4

	b	2f



1 :	.long MACH_TYPE

	.align	2

dtb_info:

	.word	dtb_info

#ifndef __ARMEB__

	.word	0xedfe0dd0		@ sig is 0xd00dfeed big endian

#else

	.word	0xd00dfeed

#endif

	.word	MEMORY_START

	.word	_edata

	.word	0x4000			@ maximum DTB size

0:

	/* Failure: Zero board ID, NULL atag/dtb */

	mov 	r7, #0

	mov	r8, #0			@ pass null pointer as atag

2 :



#endif /* CONFIG_ZBOOT_ROM */

arch/arm/mach-shmobile/clock-r8a7740.c

+2 −1
Original line number Diff line number Diff line
@@ -596,7 +596,8 @@ static struct clk_lookup lookups[] = { 
	CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),

	CLKDEV_DEV_ID("r8a7740-gether",		&mstp_clks[MSTP309]),

	CLKDEV_DEV_ID("e9a00000.sh-eth",	&mstp_clks[MSTP309]),

	CLKDEV_DEV_ID("renesas_tpu_pwm",	&mstp_clks[MSTP304]),

	CLKDEV_DEV_ID("renesas-tpu-pwm",	&mstp_clks[MSTP304]),

	CLKDEV_DEV_ID("e6600000.pwm",		&mstp_clks[MSTP304]),



	CLKDEV_DEV_ID("sh_mobile_sdhi.2",	&mstp_clks[MSTP415]),

	CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),

arch/arm/mach-shmobile/clock-r8a7790.c

+4 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ 
#define SMSTPCR3 0xe615013c

#define SMSTPCR5 0xe6150144

#define SMSTPCR7 0xe615014c

#define SMSTPCR8 0xe6150990



#define SDCKCR		0xE6150074

#define SD2CKCR		0xE6150078
@@ -180,6 +181,7 @@ static struct clk div6_clks[DIV6_NR] = { 


/* MSTP */

enum {

	MSTP813,

	MSTP721, MSTP720,

	MSTP717, MSTP716,

	MSTP522,
@@ -190,6 +192,7 @@ enum { 
};



static struct clk mstp_clks[MSTP_NR] = {

	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */

	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */

	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */

	[MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
@@ -258,6 +261,7 @@ static struct clk_lookup lookups[] = { 
	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),

	CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),

	CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),

	CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),

	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),

	CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),

	CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),

arch/arm/mach-shmobile/headsmp-scu.S

+3 −1
Original line number Diff line number Diff line
@@ -37,13 +37,15 @@ ENTRY(shmobile_boot_scu) 
	lsl	r1, r1, #3		@ we will shift by cpu_id * 8 bits

	ldr	r2, [r0, #8]		@ SCU Power Status Register

	mov	r3, #3

	bic	r2, r2, r3, lsl r1	@ Clear bits of our CPU (Run Mode)

	lsl	r3, r3, r1

	bic	r2, r2, r3		@ Clear bits of our CPU (Run Mode)

	str	r2, [r0, #8]		@ write back



	b	shmobile_invalidate_start

ENDPROC(shmobile_boot_scu)



	.text

	.align	2

	.globl	shmobile_scu_base

shmobile_scu_base:

	.space	4

arch/arm/mach-shmobile/headsmp.S

+5 −1
Original line number Diff line number Diff line
@@ -24,12 +24,16 @@ ENDPROC(shmobile_invalidate_start) 
 * This will be mapped at address 0 by SBAR register.

 * We need _long_ jump to the physical address.

 */

	.arm

	.align  12

ENTRY(shmobile_boot_vector)

	ldr     r0, 2f

	ldr     pc, 1f

	ldr     r1, 1f

	bx	r1



ENDPROC(shmobile_boot_vector)



	.align	2

	.globl	shmobile_boot_fn

shmobile_boot_fn:

1:	.space	4