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Commit f2b115e6 authored by Adam Jackson's avatar Adam Jackson Committed by Eric Anholt
Browse files

drm/i915: Fix product names and #defines 



IGD* isn't a useful name.  Replace with the codenames, as sourced from
pci.ids.

Signed-off-by: default avatarAdam Jackson <ajax@redhat.com>
[anholt: Fixed up for merge with pineview/ironlake changes]
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 107f517b

drivers/gpu/drm/i915/i915_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) 
	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;



	if (!IS_IGDNG(dev)) {

	if (!IS_IRONLAKE(dev)) {

		seq_printf(m, "Interrupt enable:    %08x\n",

			   I915_READ(IER));

		seq_printf(m, "Interrupt identity:  %08x\n",

drivers/gpu/drm/i915/i915_dma.c

+4 −4
Original line number Diff line number Diff line
@@ -968,7 +968,7 @@ static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, 
	 * Some of the preallocated space is taken by the GTT

	 * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.

	 */

	if (IS_G4X(dev) || IS_IGD(dev) || IS_IGDNG(dev))

	if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev))

		overhead = 4096;

	else

		overhead = (*aperture_size / 1024) + 4096;
@@ -1054,7 +1054,7 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev, 
	int gtt_offset, gtt_size;



	if (IS_I965G(dev)) {

		if (IS_G4X(dev) || IS_IGDNG(dev)) {

		if (IS_G4X(dev) || IS_IRONLAKE(dev)) {

			gtt_offset = 2*1024*1024;

			gtt_size = 2*1024*1024;

		} else {
@@ -1312,7 +1312,7 @@ static void i915_get_mem_freq(struct drm_device *dev) 
	drm_i915_private_t *dev_priv = dev->dev_private;

	u32 tmp;



	if (!IS_IGD(dev))

	if (!IS_PINEVIEW(dev))

		return;



	tmp = I915_READ(CLKCFG);
@@ -1440,7 +1440,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 


	dev->driver->get_vblank_counter = i915_get_vblank_counter;

	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */

	if (IS_G4X(dev) || IS_IGDNG(dev)) {

	if (IS_G4X(dev) || IS_IRONLAKE(dev)) {

		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */

		dev->driver->get_vblank_counter = gm45_get_vblank_counter;

	}

drivers/gpu/drm/i915/i915_drv.h

+22 −22
Original line number Diff line number Diff line
@@ -209,7 +209,7 @@ typedef struct drm_i915_private { 
	/** Cached value of IMR to avoid reads in updating the bitfield */

	u32 irq_mask_reg;

	u32 pipestat[2];

	/** splitted irq regs for graphics and display engine on IGDNG,

	/** splitted irq regs for graphics and display engine on Ironlake,

	    irq_mask_reg is still used for display irq. */

	u32 gt_irq_mask_reg;

	u32 gt_irq_enable_reg;
@@ -1010,51 +1010,51 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 
		     (dev)->pci_device == 0x2E42 || \

		     IS_GM45(dev))



#define IS_IGDG(dev) ((dev)->pci_device == 0xa001)

#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)

#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))

#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)

#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)

#define IS_PINEVIEW(dev) (IS_PINEVIEW_G(dev) || IS_PINEVIEW_M(dev))



#define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||	\

			(dev)->pci_device == 0x29B2 ||	\

			(dev)->pci_device == 0x29D2 ||  \

			(IS_IGD(dev)))

			(IS_PINEVIEW(dev)))



#define IS_IGDNG_D(dev)	((dev)->pci_device == 0x0042)

#define IS_IGDNG_M(dev)	((dev)->pci_device == 0x0046)

#define IS_IGDNG(dev)	(IS_IGDNG_D(dev) || IS_IGDNG_M(dev))

#define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)

#define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)

#define IS_IRONLAKE(dev)	(IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev))



#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \

		      IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \

		      IS_IGDNG(dev))

		      IS_IRONLAKE(dev))



#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \

			IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \

			IS_IGD(dev) || IS_IGDNG_M(dev))

			IS_PINEVIEW(dev) || IS_IRONLAKE_M(dev))



#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \

				IS_IGDNG(dev))

				IS_IRONLAKE(dev))

/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte

 * rows, which changed the alignment requirements and fence programming.

 */

#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \

						      IS_I915GM(dev)))

#define SUPPORTS_DIGITAL_OUTPUTS(dev)	(IS_I9XX(dev) && !IS_IGD(dev))

#define SUPPORTS_INTEGRATED_HDMI(dev)	(IS_G4X(dev) || IS_IGDNG(dev))

#define SUPPORTS_INTEGRATED_DP(dev)	(IS_G4X(dev) || IS_IGDNG(dev))

#define SUPPORTS_EDP(dev)		(IS_IGDNG_M(dev))

#define SUPPORTS_DIGITAL_OUTPUTS(dev)	(IS_I9XX(dev) && !IS_PINEVIEW(dev))

#define SUPPORTS_INTEGRATED_HDMI(dev)	(IS_G4X(dev) || IS_IRONLAKE(dev))

#define SUPPORTS_INTEGRATED_DP(dev)	(IS_G4X(dev) || IS_IRONLAKE(dev))

#define SUPPORTS_EDP(dev)		(IS_IRONLAKE_M(dev))

#define SUPPORTS_TV(dev)		(IS_I9XX(dev) && IS_MOBILE(dev) && \

					!IS_IGDNG(dev) && !IS_IGD(dev))

					!IS_IRONLAKE(dev) && !IS_PINEVIEW(dev))

#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))

/* dsparb controlled by hw only */

#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))

#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))



#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))

#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))

#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))

#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))

#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \

			   (IS_I9XX(dev) || IS_GM45(dev)) && \

			   !IS_IGD(dev) && \

			   !IS_IGDNG(dev))

#define I915_HAS_RC6(dev) (IS_I965GM(dev) || IS_GM45(dev) || IS_IGDNG_M(dev))

			   !IS_PINEVIEW(dev) && \

			   !IS_IRONLAKE(dev))

#define I915_HAS_RC6(dev) (IS_I965GM(dev) || IS_GM45(dev) || IS_IRONLAKE_M(dev))



#define PRIMARY_RINGBUFFER_SIZE         (128*1024)

drivers/gpu/drm/i915/i915_gem.c

+1 −1
Original line number Diff line number Diff line
@@ -1833,7 +1833,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible) 
		return -EIO;



	if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {

		if (IS_IGDNG(dev))

		if (IS_IRONLAKE(dev))

			ier = I915_READ(DEIER) | I915_READ(GTIER);

		else

			ier = I915_READ(IER);

drivers/gpu/drm/i915/i915_gem_tiling.c

+2 −2
Original line number Diff line number Diff line
@@ -209,8 +209,8 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) 
	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;

	bool need_disable;



	if (IS_IGDNG(dev)) {

		/* On IGDNG whatever DRAM config, GPU always do

	if (IS_IRONLAKE(dev)) {

		/* On Ironlake whatever DRAM config, GPU always do

		 * same swizzling setup.

		 */

		swizzle_x = I915_BIT_6_SWIZZLE_9_10;