Commit f1e8e381 authored Nov 08, 2013 by Sricharan R Committed by Rob Herring Dec 02, 2013

ARM: dts: doc: Document missing binding for omap5-mpu



The binding and support for omap5-mpu which has a cortex-a15
smp core, gic and integrated L2 cache has been existing for sometime.
So Documenting the missing binding here.

Cc: Benoit Cousson <bcousson@baylibre.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>

parent f04bda90

Documentation/devicetree/bindings/arm/omap/mpu.txt

+8 −0

Original line number	Diff line number	Diff line
		@@ -7,10 +7,18 @@ The MPU contain CPUs, GIC, L2 cache and a local PRCM.
		Required properties:
		- compatible : Should be "ti,omap3-mpu" for OMAP3
		Should be "ti,omap4-mpu" for OMAP4
		Should be "ti,omap5-mpu" for OMAP5
		- ti,hwmods: "mpu"

		Examples:

		- For an OMAP5 SMP system:

		mpu {
		compatible = "ti,omap5-mpu";
		ti,hwmods = "mpu"
		};

		- For an OMAP4 SMP system:

		mpu {