[PATCH] chelsio: add support for other 10G boards (f1d3d38a) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/net/Kconfig

+3 −3

Original line number	Diff line number	Diff line
		@@ -2361,9 +2361,9 @@ config CHELSIO_T1
		tristate "Chelsio 10Gb Ethernet support"
		depends on PCI
		help
		This driver supports Chelsio N110 and N210 models 10Gb Ethernet
		cards. More information about adapter features and performance
		tuning is in <file:Documentation/networking/cxgb.txt>.
		This driver supports Chelsio gigabit and 10-gigabit
		Ethernet cards. More information about adapter features and
		performance tuning is in <file:Documentation/networking/cxgb.txt>.

		For general information about Chelsio and our products, visit
		our website at <http://www.chelsio.com>.

drivers/net/chelsio/Makefile

+3 −4

Original line number	Diff line number	Diff line
		#
		# Chelsio 10Gb NIC driver for Linux.
		# Chelsio T1 driver
		#

		obj-$(CONFIG_CHELSIO_T1) += cxgb.o

		EXTRA_CFLAGS += -Idrivers/net/chelsio $(DEBUG_FLAGS)
		cxgb-objs := cxgb2.o espi.o tp.o pm3393.o sge.o subr.o \
		mv88x201x.o my3126.o $(cxgb-y)


		cxgb-objs := cxgb2.o espi.o pm3393.o sge.o subr.o mv88x201x.o

drivers/net/chelsio/common.h

+88 −13

Original line number	Diff line number	Diff line
		@@ -45,6 +45,7 @@
		#include <linux/delay.h>
		#include <linux/pci.h>
		#include <linux/ethtool.h>
		#include <linux/if_vlan.h>
		#include <linux/mii.h>
		#include <linux/crc32.h>
		#include <linux/init.h>
		@@ -53,13 +54,30 @@

		#define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
		#define DRV_NAME "cxgb"
		#define DRV_VERSION "2.1.1"
		#define DRV_VERSION "2.2"
		#define PFX DRV_NAME ": "

		#define CH_ERR(fmt, ...) printk(KERN_ERR PFX fmt, ## __VA_ARGS__)
		#define CH_WARN(fmt, ...) printk(KERN_WARNING PFX fmt, ## __VA_ARGS__)
		#define CH_ALERT(fmt, ...) printk(KERN_ALERT PFX fmt, ## __VA_ARGS__)

		/*
		* More powerful macro that selectively prints messages based on msg_enable.
		* For info and debugging messages.
		*/
		#define CH_MSG(adapter, level, category, fmt, ...) do { \
		if ((adapter)->msg_enable & NETIF_MSG_##category) \
		printk(KERN_##level PFX "%s: " fmt, (adapter)->name, \
		## __VA_ARGS__); \
		} while (0)

		#ifdef DEBUG
		# define CH_DBG(adapter, category, fmt, ...) \
		CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
		#else
		# define CH_DBG(fmt, ...)
		#endif

		#define CH_DEVICE(devid, ssid, idx) \
		{ PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }

		@@ -71,10 +89,6 @@

		typedef struct adapter adapter_t;

		void t1_elmer0_ext_intr(adapter_t *adapter);
		void t1_link_changed(adapter_t *adapter, int port_id, int link_status,
		int speed, int duplex, int fc);

		struct t1_rx_mode {
		struct net_device *dev;
		u32 idx;
		@@ -97,26 +111,53 @@ static inline u8 t1_get_next_mcaddr(struct t1_rx_mode rm)
		}

		#define MAX_NPORTS 4
		#define PORT_MASK ((1 << MAX_NPORTS) - 1)
		#define NMTUS 8
		#define TCB_SIZE 128

		#define SPEED_INVALID 0xffff
		#define DUPLEX_INVALID 0xff

		enum {
		CHBT_BOARD_N110,
		CHBT_BOARD_N210
		CHBT_BOARD_N210,
		CHBT_BOARD_7500,
		CHBT_BOARD_8000,
		CHBT_BOARD_CHT101,
		CHBT_BOARD_CHT110,
		CHBT_BOARD_CHT210,
		CHBT_BOARD_CHT204,
		CHBT_BOARD_CHT204V,
		CHBT_BOARD_CHT204E,
		CHBT_BOARD_CHN204,
		CHBT_BOARD_COUGAR,
		CHBT_BOARD_6800,
		CHBT_BOARD_SIMUL,
		};

		enum {
		CHBT_TERM_FPGA,
		CHBT_TERM_T1,
		CHBT_TERM_T2
		CHBT_TERM_T2,
		CHBT_TERM_T3
		};

		enum {
		CHBT_MAC_CHELSIO_A,
		CHBT_MAC_IXF1010,
		CHBT_MAC_PM3393,
		CHBT_MAC_VSC7321,
		CHBT_MAC_DUMMY
		};

		enum {
		CHBT_PHY_88E1041,
		CHBT_PHY_88E1111,
		CHBT_PHY_88X2010,
		CHBT_PHY_XPAK,
		CHBT_PHY_MY3126,
		CHBT_PHY_8244,
		CHBT_PHY_DUMMY
		};

		enum {
		@@ -150,16 +191,43 @@ struct chelsio_pci_params {
		unsigned char is_pcix;
		};

		struct tp_params {
		unsigned int pm_size;
		unsigned int cm_size;
		unsigned int pm_rx_base;
		unsigned int pm_tx_base;
		unsigned int pm_rx_pg_size;
		unsigned int pm_tx_pg_size;
		unsigned int pm_rx_num_pgs;
		unsigned int pm_tx_num_pgs;
		unsigned int rx_coalescing_size;
		unsigned int use_5tuple_mode;
		};

		struct mc5_params {
		unsigned int mode; /* selects MC5 width */
		unsigned int nservers; /* size of server region */
		unsigned int nroutes; /* size of routing region */
		};

		/* Default MC5 region sizes */
		#define DEFAULT_SERVER_REGION_LEN 256
		#define DEFAULT_RT_REGION_LEN 1024

		struct adapter_params {
		struct sge_params sge;
		struct mc5_params mc5;
		struct tp_params tp;
		struct chelsio_pci_params pci;

		const struct board_info *brd_info;

		unsigned short mtus[NMTUS];
		unsigned int nports; /* # of ethernet ports */
		unsigned int stats_update_period;
		unsigned short chip_revision;
		unsigned char chip_version;
		unsigned char is_asic;
		};

		struct link_config {
		@@ -207,6 +275,7 @@ struct adapter {
		/* Terminator modules. */
		struct sge *sge;
		struct peespi *espi;
		struct petp *tp;

		struct port_info port[MAX_NPORTS];
		struct work_struct stats_update_task;
		@@ -217,6 +286,7 @@ struct adapter {
		/* guards async operations */
		spinlock_t async_lock ____cacheline_aligned;
		u32 slow_intr_mask;
		int t1powersave;
		};

		enum { /* adapter flags */
		@@ -255,6 +325,11 @@ struct board_info {
		const char *desc;
		};

		static inline int t1_is_asic(const adapter_t *adapter)
		{
		return adapter->params.is_asic;
		}

		extern struct pci_device_id t1_pci_tbl[];

		static inline int adapter_matches_type(const adapter_t *adapter,
		@@ -284,13 +359,15 @@ static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
		return board_info(adap)->clock_core / 1000000;
		}

		extern int __t1_tpi_read(adapter_t adapter, u32 addr, u32 valp);
		extern int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
		extern int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
		extern int t1_tpi_read(adapter_t adapter, u32 addr, u32 value);

		extern void t1_interrupts_enable(adapter_t *adapter);
		extern void t1_interrupts_disable(adapter_t *adapter);
		extern void t1_interrupts_clear(adapter_t *adapter);
		extern int elmer0_ext_intr_handler(adapter_t *adapter);
		extern int t1_elmer0_ext_intr_handler(adapter_t *adapter);
		extern int t1_slow_intr_handler(adapter_t *adapter);

		extern int t1_link_start(struct cphy phy, struct cmac mac, struct link_config *lc);
		@@ -304,9 +381,7 @@ extern int t1_init_hw_modules(adapter_t *adapter);
		extern int t1_init_sw_modules(adapter_t adapter, const struct board_info bi);
		extern void t1_free_sw_modules(adapter_t *adapter);
		extern void t1_fatal_err(adapter_t *adapter);

		extern void t1_tp_set_udp_checksum_offload(adapter_t *adapter, int enable);
		extern void t1_tp_set_tcp_checksum_offload(adapter_t *adapter, int enable);
		extern void t1_tp_set_ip_checksum_offload(adapter_t *adapter, int enable);

		extern void t1_link_changed(adapter_t *adapter, int port_id);
		extern void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat,
		int speed, int duplex, int pause);
		#endif /* _CXGB_COMMON_H_ */

drivers/net/chelsio/cphy.h

+23 −1

Original line number	Diff line number	Diff line
		@@ -52,7 +52,14 @@ struct mdio_ops {
		/* PHY interrupt types */
		enum {
		cphy_cause_link_change = 0x1,
		cphy_cause_error = 0x2
		cphy_cause_error = 0x2,
		cphy_cause_fifo_error = 0x3
		};

		enum {
		PHY_LINK_UP = 0x1,
		PHY_AUTONEG_RDY = 0x2,
		PHY_AUTONEG_EN = 0x4
		};

		struct cphy;
		@@ -81,7 +88,18 @@ struct cphy_ops {
		/* A PHY instance */
		struct cphy {
		int addr; /* PHY address */
		int state; /* Link status state machine */
		adapter_t adapter; / associated adapter */

		struct work_struct phy_update;

		u16 bmsr;
		int count;
		int act_count;
		int act_on;

		u32 elmer_gpo;

		struct cphy_ops ops; / PHY operations */
		int (mdio_read)(adapter_t adapter, int phy_addr, int mmd_addr,
		int reg_addr, unsigned int *val);
		@@ -142,6 +160,10 @@ struct gphy {
		int (reset)(adapter_t adapter);
		};

		extern struct gphy t1_my3126_ops;
		extern struct gphy t1_mv88e1xxx_ops;
		extern struct gphy t1_vsc8244_ops;
		extern struct gphy t1_xpak_ops;
		extern struct gphy t1_mv88x201x_ops;
		extern struct gphy t1_dummy_phy_ops;

drivers/net/chelsio/cpl5_cmd.h

+502 −8

Original line number	Diff line number	Diff line
		@@ -46,24 +46,385 @@
		#endif

		enum CPL_opcode {
		CPL_PASS_OPEN_REQ = 0x1,
		CPL_PASS_OPEN_RPL = 0x2,
		CPL_PASS_ESTABLISH = 0x3,
		CPL_PASS_ACCEPT_REQ = 0xE,
		CPL_PASS_ACCEPT_RPL = 0x4,
		CPL_ACT_OPEN_REQ = 0x5,
		CPL_ACT_OPEN_RPL = 0x6,
		CPL_CLOSE_CON_REQ = 0x7,
		CPL_CLOSE_CON_RPL = 0x8,
		CPL_CLOSE_LISTSRV_REQ = 0x9,
		CPL_CLOSE_LISTSRV_RPL = 0xA,
		CPL_ABORT_REQ = 0xB,
		CPL_ABORT_RPL = 0xC,
		CPL_PEER_CLOSE = 0xD,
		CPL_ACT_ESTABLISH = 0x17,

		CPL_GET_TCB = 0x24,
		CPL_GET_TCB_RPL = 0x25,
		CPL_SET_TCB = 0x26,
		CPL_SET_TCB_FIELD = 0x27,
		CPL_SET_TCB_RPL = 0x28,
		CPL_PCMD = 0x29,

		CPL_PCMD_READ = 0x31,
		CPL_PCMD_READ_RPL = 0x32,


		CPL_RX_DATA = 0xA0,
		CPL_RX_DATA_DDP = 0xA1,
		CPL_RX_DATA_ACK = 0xA3,
		CPL_RX_PKT = 0xAD,
		CPL_RX_ISCSI_HDR = 0xAF,
		CPL_TX_DATA_ACK = 0xB0,
		CPL_TX_DATA = 0xB1,
		CPL_TX_PKT = 0xB2,
		CPL_TX_PKT_LSO = 0xB6,

		CPL_RTE_DELETE_REQ = 0xC0,
		CPL_RTE_DELETE_RPL = 0xC1,
		CPL_RTE_WRITE_REQ = 0xC2,
		CPL_RTE_WRITE_RPL = 0xD3,
		CPL_RTE_READ_REQ = 0xC3,
		CPL_RTE_READ_RPL = 0xC4,
		CPL_L2T_WRITE_REQ = 0xC5,
		CPL_L2T_WRITE_RPL = 0xD4,
		CPL_L2T_READ_REQ = 0xC6,
		CPL_L2T_READ_RPL = 0xC7,
		CPL_SMT_WRITE_REQ = 0xC8,
		CPL_SMT_WRITE_RPL = 0xD5,
		CPL_SMT_READ_REQ = 0xC9,
		CPL_SMT_READ_RPL = 0xCA,
		CPL_ARP_MISS_REQ = 0xCD,
		CPL_ARP_MISS_RPL = 0xCE,
		CPL_MIGRATE_C2T_REQ = 0xDC,
		CPL_MIGRATE_C2T_RPL = 0xDD,
		CPL_ERROR = 0xD7,

		/* internal: driver -> TOM */
		CPL_MSS_CHANGE = 0xE1
		};

		#define NUM_CPL_CMDS 256

		enum CPL_error {
		CPL_ERR_NONE = 0,
		CPL_ERR_TCAM_PARITY = 1,
		CPL_ERR_TCAM_FULL = 3,
		CPL_ERR_CONN_RESET = 20,
		CPL_ERR_CONN_EXIST = 22,
		CPL_ERR_ARP_MISS = 23,
		CPL_ERR_BAD_SYN = 24,
		CPL_ERR_CONN_TIMEDOUT = 30,
		CPL_ERR_XMIT_TIMEDOUT = 31,
		CPL_ERR_PERSIST_TIMEDOUT = 32,
		CPL_ERR_FINWAIT2_TIMEDOUT = 33,
		CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
		CPL_ERR_ABORT_FAILED = 42,
		CPL_ERR_GENERAL = 99
		};

		enum {
		CPL_CONN_POLICY_AUTO = 0,
		CPL_CONN_POLICY_ASK = 1,
		CPL_CONN_POLICY_DENY = 3
		};

		enum { /* TX_PKT_LSO ethernet types */
		enum {
		ULP_MODE_NONE = 0,
		ULP_MODE_TCPDDP = 1,
		ULP_MODE_ISCSI = 2,
		ULP_MODE_IWARP = 3,
		ULP_MODE_SSL = 4
		};

		enum {
		CPL_PASS_OPEN_ACCEPT,
		CPL_PASS_OPEN_REJECT
		};

		enum {
		CPL_ABORT_SEND_RST = 0,
		CPL_ABORT_NO_RST,
		CPL_ABORT_POST_CLOSE_REQ = 2
		};

		enum { // TX_PKT_LSO ethernet types
		CPL_ETH_II,
		CPL_ETH_II_VLAN,
		CPL_ETH_802_3,
		CPL_ETH_802_3_VLAN
		};

		struct cpl_rx_data {
		union opcode_tid {
		u32 opcode_tid;
		u8 opcode;
		};

		#define S_OPCODE 24
		#define V_OPCODE(x) ((x) << S_OPCODE)
		#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
		#define G_TID(x) ((x) & 0xFFFFFF)

		/* tid is assumed to be 24-bits */
		#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) \| (tid))

		#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)

		/* extract the TID from a CPL command */
		#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))

		struct tcp_options {
		u16 mss;
		u8 wsf;
		#if defined(__LITTLE_ENDIAN_BITFIELD)
		u8 rsvd:4;
		u8 ecn:1;
		u8 sack:1;
		u8 tstamp:1;
		#else
		u8 tstamp:1;
		u8 sack:1;
		u8 ecn:1;
		u8 rsvd:4;
		#endif
		};

		struct cpl_pass_open_req {
		union opcode_tid ot;
		u16 local_port;
		u16 peer_port;
		u32 local_ip;
		u32 peer_ip;
		u32 opt0h;
		u32 opt0l;
		u32 peer_netmask;
		u32 opt1;
		};

		struct cpl_pass_open_rpl {
		union opcode_tid ot;
		u16 local_port;
		u16 peer_port;
		u32 local_ip;
		u32 peer_ip;
		u8 resvd[7];
		u8 status;
		};

		struct cpl_pass_establish {
		union opcode_tid ot;
		u16 local_port;
		u16 peer_port;
		u32 local_ip;
		u32 peer_ip;
		u32 tos_tid;
		u8 l2t_idx;
		u8 rsvd[3];
		u32 snd_isn;
		u32 rcv_isn;
		};

		struct cpl_pass_accept_req {
		union opcode_tid ot;
		u16 local_port;
		u16 peer_port;
		u32 local_ip;
		u32 peer_ip;
		u32 tos_tid;
		struct tcp_options tcp_options;
		u8 dst_mac[6];
		u16 vlan_tag;
		u8 src_mac[6];
		u8 rsvd[2];
		u32 rcv_isn;
		u32 unknown_tcp_options;
		};

		struct cpl_pass_accept_rpl {
		union opcode_tid ot;
		u32 rsvd0;
		u32 rsvd1;
		u32 peer_ip;
		u32 opt0h;
		union {
		u32 opt0l;
		struct {
		u8 rsvd[3];
		u8 status;
		};
		};
		};

		struct cpl_act_open_req {
		union opcode_tid ot;
		u16 local_port;
		u16 peer_port;
		u32 local_ip;
		u32 peer_ip;
		u32 opt0h;
		u32 opt0l;
		u32 iff_vlantag;
		u32 rsvd;
		};

		struct cpl_act_open_rpl {
		union opcode_tid ot;
		u16 local_port;
		u16 peer_port;
		u32 local_ip;
		u32 peer_ip;
		u32 new_tid;
		u8 rsvd[3];
		u8 status;
		};

		struct cpl_act_establish {
		union opcode_tid ot;
		u16 local_port;
		u16 peer_port;
		u32 local_ip;
		u32 peer_ip;
		u32 tos_tid;
		u32 rsvd;
		u32 snd_isn;
		u32 rcv_isn;
		};

		struct cpl_get_tcb {
		union opcode_tid ot;
		u32 rsvd;
		};

		struct cpl_get_tcb_rpl {
		union opcode_tid ot;
		u16 len;
		u8 rsvd;
		u8 status;
		};

		struct cpl_set_tcb {
		union opcode_tid ot;
		u16 len;
		u16 rsvd;
		};

		struct cpl_set_tcb_field {
		union opcode_tid ot;
		u8 rsvd[3];
		u8 offset;
		u32 mask;
		u32 val;
		};

		struct cpl_set_tcb_rpl {
		union opcode_tid ot;
		u8 rsvd[3];
		u8 status;
		};

		struct cpl_pcmd {
		union opcode_tid ot;
		u16 dlen_in;
		u16 dlen_out;
		u32 pcmd_parm[2];
		};

		struct cpl_pcmd_read {
		union opcode_tid ot;
		u32 rsvd1;
		u16 rsvd2;
		u32 addr;
		u16 len;
		};

		struct cpl_pcmd_read_rpl {
		union opcode_tid ot;
		u16 len;
		};

		struct cpl_close_con_req {
		union opcode_tid ot;
		u32 rsvd;
		};

		struct cpl_close_con_rpl {
		union opcode_tid ot;
		u8 rsvd[3];
		u8 status;
		u32 snd_nxt;
		u32 rcv_nxt;
		};

		struct cpl_close_listserv_req {
		union opcode_tid ot;
		u32 rsvd;
		};

		struct cpl_close_listserv_rpl {
		union opcode_tid ot;
		u8 rsvd[3];
		u8 status;
		};

		struct cpl_abort_req {
		union opcode_tid ot;
		u32 rsvd0;
		u8 rsvd1;
		u8 cmd;
		u8 rsvd2[6];
		};

		struct cpl_abort_rpl {
		union opcode_tid ot;
		u32 rsvd0;
		u8 rsvd1;
		u8 status;
		u8 rsvd2[6];
		};

		struct cpl_peer_close {
		union opcode_tid ot;
		u32 rsvd;
		};

		struct cpl_tx_data {
		union opcode_tid ot;
		u32 len;
		u32 rsvd0;
		u16 urg;
		u16 flags;
		};

		struct cpl_tx_data_ack {
		union opcode_tid ot;
		u32 ack_seq;
		};

		struct cpl_rx_data {
		union opcode_tid ot;
		u32 len;
		u32 seq;
		u16 urg;
		u8 rsvd1;
		u8 rsvd;
		u8 status;
		};

		struct cpl_rx_data_ack {
		union opcode_tid ot;
		u32 credit;
		};

		struct cpl_rx_data_ddp {
		union opcode_tid ot;
		u32 len;
		u32 seq;
		u32 nxt_seq;
		u32 ulp_crc;
		u16 ddp_status;
		u8 rsvd;
		u8 status;
		};

		@@ -99,9 +460,9 @@ struct cpl_tx_pkt_lso {
		u8 ip_csum_dis:1;
		u8 l4_csum_dis:1;
		u8 vlan_valid:1;
		u8 rsvd:1;
		u8 :1;
		#else
		u8 rsvd:1;
		u8 :1;
		u8 vlan_valid:1;
		u8 l4_csum_dis:1;
		u8 ip_csum_dis:1;
		@@ -110,8 +471,7 @@ struct cpl_tx_pkt_lso {
		u16 vlan;
		__be32 len;

		u32 rsvd2;
		u8 rsvd3;
		u8 rsvd[5];
		#if defined(__LITTLE_ENDIAN_BITFIELD)
		u8 tcp_hdr_words:4;
		u8 ip_hdr_words:4;
		@@ -138,8 +498,142 @@ struct cpl_rx_pkt {
		u8 iff:4;
		#endif
		u16 csum;
		__be16 vlan;
		u16 vlan;
		u16 len;
		};

		struct cpl_l2t_write_req {
		union opcode_tid ot;
		u32 params;
		u8 rsvd1[2];
		u8 dst_mac[6];
		};

		struct cpl_l2t_write_rpl {
		union opcode_tid ot;
		u8 status;
		u8 rsvd[3];
		};

		struct cpl_l2t_read_req {
		union opcode_tid ot;
		u8 rsvd[3];
		u8 l2t_idx;
		};

		struct cpl_l2t_read_rpl {
		union opcode_tid ot;
		u32 params;
		u8 rsvd1[2];
		u8 dst_mac[6];
		};

		struct cpl_smt_write_req {
		union opcode_tid ot;
		u8 rsvd0;
		#if defined(__LITTLE_ENDIAN_BITFIELD)
		u8 rsvd1:1;
		u8 mtu_idx:3;
		u8 iff:4;
		#else
		u8 iff:4;
		u8 mtu_idx:3;
		u8 rsvd1:1;
		#endif
		u16 rsvd2;
		u16 rsvd3;
		u8 src_mac1[6];
		u16 rsvd4;
		u8 src_mac0[6];
		};

		struct cpl_smt_write_rpl {
		union opcode_tid ot;
		u8 status;
		u8 rsvd[3];
		};

		struct cpl_smt_read_req {
		union opcode_tid ot;
		u8 rsvd0;
		#if defined(__LITTLE_ENDIAN_BITFIELD)
		u8 rsvd1:4;
		u8 iff:4;
		#else
		u8 iff:4;
		u8 rsvd1:4;
		#endif
		u16 rsvd2;
		};

		struct cpl_smt_read_rpl {
		union opcode_tid ot;
		u8 status;
		#if defined(__LITTLE_ENDIAN_BITFIELD)
		u8 rsvd1:1;
		u8 mtu_idx:3;
		u8 rsvd0:4;
		#else
		u8 rsvd0:4;
		u8 mtu_idx:3;
		u8 rsvd1:1;
		#endif
		u16 rsvd2;
		u16 rsvd3;
		u8 src_mac1[6];
		u16 rsvd4;
		u8 src_mac0[6];
		};

		struct cpl_rte_delete_req {
		union opcode_tid ot;
		u32 params;
		};

		struct cpl_rte_delete_rpl {
		union opcode_tid ot;
		u8 status;
		u8 rsvd[3];
		};

		struct cpl_rte_write_req {
		union opcode_tid ot;
		u32 params;
		u32 netmask;
		u32 faddr;
		};

		struct cpl_rte_write_rpl {
		union opcode_tid ot;
		u8 status;
		u8 rsvd[3];
		};

		struct cpl_rte_read_req {
		union opcode_tid ot;
		u32 params;
		};

		struct cpl_rte_read_rpl {
		union opcode_tid ot;
		u8 status;
		u8 rsvd0[2];
		u8 l2t_idx;
		#if defined(__LITTLE_ENDIAN_BITFIELD)
		u8 rsvd1:7;
		u8 select:1;
		#else
		u8 select:1;
		u8 rsvd1:7;
		#endif
		u8 rsvd2[3];
		u32 addr;
		};

		struct cpl_mss_change {
		union opcode_tid ot;
		u32 mss;
		};

		#endif /* _CXGB_CPL5_CMD_H_ */