Loading arch/arm/boot/dts/qcom/msmtitanium.dtsi +25 −0 Original line number Diff line number Diff line Loading @@ -1390,6 +1390,30 @@ }; }; sdcc1_ice: sdcc1ice@7803000 { compatible = "qcom,ice"; reg = <0x7803000 0x8000>; interrupt-names = "sdcc_ice_nonsec_level_irq", "sdcc_ice_sec_level_irq"; interrupts = <0 312 0>, <0 313 0>; qcom,enable-ice-clk; clock-names = "ice_core_clk_src", "ice_core_clk", "bus_clk", "iface_clk"; clocks = <&clock_gcc clk_sdcc1_ice_core_clk_src>, <&clock_gcc clk_gcc_sdcc1_ice_core_clk>, <&clock_gcc clk_gcc_sdcc1_apps_clk>, <&clock_gcc clk_gcc_sdcc1_ahb_clk>; qcom,op-freq-hz = <270000000>, <0>, <0>, <0>; qcom,msm-bus,name = "sdcc_ice_noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ <78 512 1000 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "MAX"; qcom,instance-type = "sdcc"; }; sdhc_1: sdhci@7824900 { compatible = "qcom,sdhci-msm"; reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>; Loading @@ -1398,6 +1422,7 @@ interrupts = <0 123 0>, <0 138 0>; interrupt-names = "hc_irq", "pwr_irq"; sdhc-msm-crypto = <&sdcc1_ice>; qcom,bus-width = <8>; qcom,devfreq,freq-table = <50000000 200000000>; Loading arch/arm/configs/msmcortex-perf_defconfig +2 −0 Original line number Diff line number Diff line Loading @@ -440,6 +440,8 @@ CONFIG_MMC_TEST=m CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y CONFIG_MMC_SDHCI_MSM_ICE=y CONFIG_MMC_CQ_HCI=y CONFIG_LEDS_QPNP=y CONFIG_LEDS_QPNP_FLASH=y CONFIG_LEDS_QPNP_WLED=y Loading arch/arm/configs/msmcortex_defconfig +2 −0 Original line number Diff line number Diff line Loading @@ -439,6 +439,8 @@ CONFIG_MMC_TEST=m CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y CONFIG_MMC_SDHCI_MSM_ICE=y CONFIG_MMC_CQ_HCI=y CONFIG_LEDS_QPNP=y CONFIG_LEDS_QPNP_FLASH=y CONFIG_LEDS_QPNP_WLED=y Loading Loading
arch/arm/boot/dts/qcom/msmtitanium.dtsi +25 −0 Original line number Diff line number Diff line Loading @@ -1390,6 +1390,30 @@ }; }; sdcc1_ice: sdcc1ice@7803000 { compatible = "qcom,ice"; reg = <0x7803000 0x8000>; interrupt-names = "sdcc_ice_nonsec_level_irq", "sdcc_ice_sec_level_irq"; interrupts = <0 312 0>, <0 313 0>; qcom,enable-ice-clk; clock-names = "ice_core_clk_src", "ice_core_clk", "bus_clk", "iface_clk"; clocks = <&clock_gcc clk_sdcc1_ice_core_clk_src>, <&clock_gcc clk_gcc_sdcc1_ice_core_clk>, <&clock_gcc clk_gcc_sdcc1_apps_clk>, <&clock_gcc clk_gcc_sdcc1_ahb_clk>; qcom,op-freq-hz = <270000000>, <0>, <0>, <0>; qcom,msm-bus,name = "sdcc_ice_noc"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ <78 512 1000 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "MAX"; qcom,instance-type = "sdcc"; }; sdhc_1: sdhci@7824900 { compatible = "qcom,sdhci-msm"; reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>; Loading @@ -1398,6 +1422,7 @@ interrupts = <0 123 0>, <0 138 0>; interrupt-names = "hc_irq", "pwr_irq"; sdhc-msm-crypto = <&sdcc1_ice>; qcom,bus-width = <8>; qcom,devfreq,freq-table = <50000000 200000000>; Loading
arch/arm/configs/msmcortex-perf_defconfig +2 −0 Original line number Diff line number Diff line Loading @@ -440,6 +440,8 @@ CONFIG_MMC_TEST=m CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y CONFIG_MMC_SDHCI_MSM_ICE=y CONFIG_MMC_CQ_HCI=y CONFIG_LEDS_QPNP=y CONFIG_LEDS_QPNP_FLASH=y CONFIG_LEDS_QPNP_WLED=y Loading
arch/arm/configs/msmcortex_defconfig +2 −0 Original line number Diff line number Diff line Loading @@ -439,6 +439,8 @@ CONFIG_MMC_TEST=m CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y CONFIG_MMC_SDHCI_MSM_ICE=y CONFIG_MMC_CQ_HCI=y CONFIG_LEDS_QPNP=y CONFIG_LEDS_QPNP_FLASH=y CONFIG_LEDS_QPNP_WLED=y Loading