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Commit f142e5ee authored by Marc Zyngier's avatar Marc Zyngier
Browse files

arm64: KVM: add missing dsb before invalidating Stage-2 TLBs 



When performing a Stage-2 TLB invalidation, it is necessary to
make sure the write to the page tables is observable by all CPUs.

For this purpose, add dsb instructions to __kvm_tlb_flush_vmid_ipa
and __kvm_flush_vm_context before doing the TLB invalidation itself.

Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 1bbd8054

arch/arm64/kvm/hyp.S

+3 −0
Original line number Original line Diff line number Diff line
@@ -604,6 +604,8 @@ END(__kvm_vcpu_run) 




// void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);

// void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);

ENTRY(__kvm_tlb_flush_vmid_ipa)

ENTRY(__kvm_tlb_flush_vmid_ipa)

	dsb	ishst



	kern_hyp_va	x0

	kern_hyp_va	x0

	ldr	x2, [x0, #KVM_VTTBR]

	ldr	x2, [x0, #KVM_VTTBR]

	msr	vttbr_el2, x2

	msr	vttbr_el2, x2
@@ -625,6 +627,7 @@ ENTRY(__kvm_tlb_flush_vmid_ipa) 
ENDPROC(__kvm_tlb_flush_vmid_ipa)

ENDPROC(__kvm_tlb_flush_vmid_ipa)





ENTRY(__kvm_flush_vm_context)

ENTRY(__kvm_flush_vm_context)

	dsb	ishst

	tlbi	alle1is

	tlbi	alle1is

	ic	ialluis

	ic	ialluis

	dsb	sy

	dsb	sy