ARM: dts: msm: Add GPU properties for msmtitanium

/* Copyright (c) 2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

&soc {

	msm_bus: qcom,kgsl-busmon {

		label = "kgsl-busmon";

		compatible = "qcom,kgsl-busmon";

	};

	gpubw: qcom,gpubw {

		compatible = "qcom,devbw";

		governor = "bw_vbif";

		qcom,src-dst-ports = <26 512>;

		/*

		 * active-only flag is used while registering the bus

		 * governor.It helps release the bus vote when the CPU

		 * subsystem is inactiv3

		 */

		qcom,active-only;

		qcom,bw-tbl =

			< 0    >, /*  off */

			< 1611 >, /* 1. DDR:211.20 MHz BIMC: 105.60 MHz */

			< 2124 >, /* 2. DDR:278.40 MHz BIMC: 139.20 MHz */

			< 2929 >, /* 3. DDR:384.00 MHz BIMC: 192.00 MHz */

			< 3222 >, /* 4. DDR:422.40 MHz BIMC: 211.20 MHz */

			< 4248 >, /* 5. DDR:556.80 MHz BIMC: 278.40 MHz */

			< 5126 >, /* 6. DDR:672.00 MHz BIMC: 336.00 MHz */

			< 5859 >, /* 7. DDR:768.00 MHz BIMC: 384.00 MHz */

			< 6152 >, /* 8. DDR:806.40 MHz BIMC: 403.20 MHz */

			< 6445 >, /* 9. DDR:844.80 MHz BIMC: 422.40 MHz */

			< 7104 >; /*10. DDR:931.20 MHz BIMC: 465.60 MHz */

	};

	msm_gpu: qcom,kgsl-3d0@1c00000 {

		label = "kgsl-3d0";

		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";

		status = "ok";

		reg = <0x1c00000 0x40000>;

		reg-names = "kgsl_3d0_reg_memory";

		interrupts = <0 33 0>;

		interrupt-names = "kgsl_3d0_irq";

		qcom,id = <0>;

		qcom,chipid = <0x05000600>;

		qcom,initial-pwrlevel = <2>;

		qcom,idle-timeout = <8>; //<HZ/12>

		/*

		 * Timeout to enter deeper power saving state

		 * from NAP.

		 */

		qcom,deep-nap-timeout = <2>; //<HZ/50>

		qcom,strtstp-sleepwake;

		/*

		* Clocks = KGSL_CLK_CORE | KGSL_CLK_IFACE |

		* KGSL_CLK_MEM_IFACE | KGSL_CLK_RBBMTIMER |

		* KGSL_CLK_ALWAYSON

		*/

		qcom,clk-map = <0x00000896>;

		clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>,

			<&clock_gcc clk_gcc_oxili_ahb_clk>,

			<&clock_gcc clk_gcc_bimc_gfx_clk>,

			<&clock_gcc clk_gcc_oxili_timer_clk>,

			<&clock_gcc clk_gcc_oxili_aon_clk>;

		clock-names = "core_clk", "iface_clk",

			      "mem_iface_clk", "rbbmtimer_clk", "alwayson_clk";

		/* Bus Scale Settings */

		qcom,gpubw-dev = <&gpubw>;

		qcom,bus-control;

		qcom,bus-width = <16>;

		qcom,msm-bus,name = "grp3d";

		qcom,msm-bus,num-cases = <11>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<26 512 0 0>,	     /*  off          */

				<26 512 0 1689600>, /* 1. 211.20 MHz */

				<26 512 0 2227200>, /* 2. 278.40 MHz */

				<26 512 0 3072000>, /* 3. 384.00 MHz */

				<26 512 0 3379200>, /* 4.  422.40 MHz */

				<26 512 0 4454400>, /* 5. 556.80 MHz */

				<26 512 0 5376000>, /* 6. 672.00 MHz */

				<26 512 0 6144000>, /* 7. 768.00 MHz */

				<26 512 0 6451200>, /* 8. 806.40 MHz */

				<26 512 0 6758400>, /* 9. 844.80 MHz */

				<26 512 0 7449600>; /*10. 931.20 MHz */

		/* GDSC regulator names */

		regulator-names = "vddcx", "vdd";

		/* GDSC oxili regulators */

		vddcx-supply = <&gdsc_oxili_cx>;

		vdd-supply = <&gdsc_oxili_gx>;

		/* CPU latency parameter */

		qcom,pm-qos-active-latency = <360>;

		qcom,pm-qos-wakeup-latency = <360>;

		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-pwrlevels";

			/* TURBO */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <650000000>;

				qcom,bus-freq = <9>;

				qcom,bus-min = <9>;

				qcom,bus-max = <10>;

			};

			/* NOM+ */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <560000000>;

				qcom,bus-freq = <9>;

				qcom,bus-min = <8>;

				qcom,bus-max = <10>;

			};

			/* NOM */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <510000000>;

				qcom,bus-freq = <8>;

				qcom,bus-min = <6>;

				qcom,bus-max = <10>;

			};

			/* SVS+ */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <400000000>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <9>;

			};

			/* SVS */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <320000000>;

				qcom,bus-freq = <5>;

				qcom,bus-min = <4>;

				qcom,bus-max = <7>;

			};

		       /* Low SVS */

			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <216000000>;

				qcom,bus-freq = <4>;

				qcom,bus-min = <2>;

				qcom,bus-max = <5>;

			};

		       /* Min SVS */

			qcom,gpu-pwrlevel@6 {

				reg = <6>;

				qcom,gpu-freq = <133330000>;

				qcom,bus-freq = <4>;

				qcom,bus-min = <2>;

				qcom,bus-max = <5>;

			};

			/* XO */

			qcom,gpu-pwrlevel@7 {

				reg = <7>;

				qcom,gpu-freq = <19200000>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};

	};

	kgsl_msm_iommu: qcom,kgsl-iommu@1c40000 {

		compatible = "qcom,kgsl-smmu-v2";

		reg = <0x1c40000 0x10000>;

		qcom,protect = <0x40000 0x10000>;

		qcom,micro-mmu-control = <0x6000>;

		clocks = <&clock_gcc clk_gcc_oxili_ahb_clk>,

			 <&clock_gcc clk_gcc_bimc_gfx_clk>;

		clock-names = "gpu_ahb_clk", "gcc_bimc_gfx_clk";

		qcom,secure_align_mask = <0xfff>;

		qcom,retention;

		gfx3d_user: gfx3d_user {

			compatible = "qcom,smmu-kgsl-cb";

			label = "gfx3d_user";

			iommus = <&kgsl_smmu 0>;

			qcom,gpu-offset = <0x48000>;

		};

	};

};

#include "msmtitanium-pinctrl.dtsi"

#include "msmtitanium-cpu.dtsi"

#include "msmtitanium-gpu.dtsi"

#include "msmtitanium-ion.dtsi"

#include "msmtitanium-smp2p.dtsi"

#include "msm-arm-smmu-titanium.dtsi"