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Commit f00e756e authored by Jason Gunthorpe's avatar Jason Gunthorpe Committed by David S. Miller
Browse files

dt: Document a compatible entry for MDIO ethernet Phys 



This describes a compatible entry of the form:
  ethernet-phy-idAAAA,BBBB
Which is modelled after the PCI structured compatible entry
(pciVVVV,DDDD.SSSS.ssss.RR)

If present the OF core will be able to use this information to
directly create the correct phy without auto probing the bus.

Signed-off-by: default avatarJason Gunthorpe <jgunthorpe@obsidianresearch.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 418ebec0

Documentation/devicetree/bindings/net/phy.txt

+9 −1
Original line number Diff line number Diff line
@@ -21,10 +21,18 @@ Optional Properties: 
  elements.

- max-speed: Maximum PHY supported speed (10, 100, 1000...)



  If the phy's identifier is known then the list may contain an entry

  of the form: "ethernet-phy-idAAAA.BBBB" where

     AAAA - The value of the 16 bit Phy Identifier 1 register as

            4 hex digits. This is the chip vendor OUI bits 3:18

     BBBB - The value of the 16 bit Phy Identifier 2 register as

            4 hex digits. This is the chip vendor OUI bits 19:24,

            followed by 10 bits of a vendor specific ID.



Example:



ethernet-phy@0 {

	compatible = "ethernet-phy-ieee802.3-c22";

	compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22";

	interrupt-parent = <40000>;

	interrupts = <35 1>;

	reg = <0>;