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Commit ef7d64e5 authored by Ilia Mirkin's avatar Ilia Mirkin Committed by Ben Skeggs
Browse files

drm/nouveau/vdec: implement support for VP3 engines 



For NV98+, BSP/VP/PPP are all FUC-based engines. Hook them all up in the
same way as NVC0, but with a couple of different values. Also make sure
that the PPP engine is handled in the fifo/mc/vm.

Signed-off-by: default avatarIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 57be046e

drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c

+35 −17
Original line number Diff line number Diff line
@@ -19,16 +19,14 @@ 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs

 * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin

 */



#include <core/engctx.h>

#include <core/class.h>



#include <engine/falcon.h>

#include <engine/bsp.h>



struct nv98_bsp_priv {

	struct nouveau_engine base;

	struct nouveau_falcon base;

};



/*******************************************************************************
@@ -37,30 +35,48 @@ struct nv98_bsp_priv { 


static struct nouveau_oclass

nv98_bsp_sclass[] = {

	{ 0x88b1, &nouveau_object_ofuncs },

	{ 0x85b1, &nouveau_object_ofuncs },

	{ 0x86b1, &nouveau_object_ofuncs },

	{},

};



/*******************************************************************************

 * BSP context

 * PBSP context

 ******************************************************************************/



static struct nouveau_oclass

nv98_bsp_cclass = {

	.handle = NV_ENGCTX(BSP, 0x98),

	.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = _nouveau_engctx_ctor,

		.dtor = _nouveau_engctx_dtor,

		.init = _nouveau_engctx_init,

		.fini = _nouveau_engctx_fini,

		.rd32 = _nouveau_engctx_rd32,

		.wr32 = _nouveau_engctx_wr32,

		.ctor = _nouveau_falcon_context_ctor,

		.dtor = _nouveau_falcon_context_dtor,

		.init = _nouveau_falcon_context_init,

		.fini = _nouveau_falcon_context_fini,

		.rd32 = _nouveau_falcon_context_rd32,

		.wr32 = _nouveau_falcon_context_wr32,

	},

};



/*******************************************************************************

 * BSP engine/subdev functions

 * PBSP engine/subdev functions

 ******************************************************************************/



static int

nv98_bsp_init(struct nouveau_object *object)

{

	struct nv98_bsp_priv *priv = (void *)object;

	int ret;



	ret = nouveau_falcon_init(&priv->base);

	if (ret)

		return ret;



	nv_wr32(priv, 0x084010, 0x0000ffd2);

	nv_wr32(priv, 0x08401c, 0x0000fff2);

	return 0;

}



static int

nv98_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,

	      struct nouveau_oclass *oclass, void *data, u32 size,
@@ -69,7 +85,7 @@ nv98_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 
	struct nv98_bsp_priv *priv;

	int ret;



	ret = nouveau_engine_create(parent, engine, oclass, true,

	ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,

				    "PBSP", "bsp", &priv);

	*pobject = nv_object(priv);

	if (ret)
@@ -86,8 +102,10 @@ nv98_bsp_oclass = { 
	.handle = NV_ENGINE(BSP, 0x98),

	.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = nv98_bsp_ctor,

		.dtor = _nouveau_engine_dtor,

		.init = _nouveau_engine_init,

		.fini = _nouveau_engine_fini,

		.dtor = _nouveau_falcon_dtor,

		.init = nv98_bsp_init,

		.fini = _nouveau_falcon_fini,

		.rd32 = _nouveau_falcon_rd32,

		.wr32 = _nouveau_falcon_wr32,

	},

};

drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c

+2 −0
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ nv84_fifo_context_attach(struct nouveau_object *parent, 
	case NVDEV_ENGINE_SW   : return 0;

	case NVDEV_ENGINE_GR   : addr = 0x0020; break;

	case NVDEV_ENGINE_VP   : addr = 0x0040; break;

	case NVDEV_ENGINE_PPP  :

	case NVDEV_ENGINE_MPEG : addr = 0x0060; break;

	case NVDEV_ENGINE_BSP  : addr = 0x0080; break;

	case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
@@ -91,6 +92,7 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend, 
	case NVDEV_ENGINE_SW   : return 0;

	case NVDEV_ENGINE_GR   : engn = 0; addr = 0x0020; break;

	case NVDEV_ENGINE_VP   : engn = 3; addr = 0x0040; break;

	case NVDEV_ENGINE_PPP  :

	case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;

	case NVDEV_ENGINE_BSP  : engn = 5; addr = 0x0080; break;

	case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;

drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c

+32 −20
Original line number Diff line number Diff line
@@ -19,21 +19,14 @@ 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs

 * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin

 */



#include <core/engine.h>

#include <core/engctx.h>

#include <core/class.h>



#include <engine/falcon.h>

#include <engine/ppp.h>



struct nv98_ppp_priv {

	struct nouveau_engine base;

};



struct nv98_ppp_chan {

	struct nouveau_engctx base;

	struct nouveau_falcon base;

};



/*******************************************************************************
@@ -42,6 +35,8 @@ struct nv98_ppp_chan { 


static struct nouveau_oclass

nv98_ppp_sclass[] = {

	{ 0x88b3, &nouveau_object_ofuncs },

	{ 0x85b3, &nouveau_object_ofuncs },

	{},

};
@@ -53,12 +48,12 @@ static struct nouveau_oclass 
nv98_ppp_cclass = {

	.handle = NV_ENGCTX(PPP, 0x98),

	.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = _nouveau_engctx_ctor,

		.dtor = _nouveau_engctx_dtor,

		.init = _nouveau_engctx_init,

		.fini = _nouveau_engctx_fini,

		.rd32 = _nouveau_engctx_rd32,

		.wr32 = _nouveau_engctx_wr32,

		.ctor = _nouveau_falcon_context_ctor,

		.dtor = _nouveau_falcon_context_dtor,

		.init = _nouveau_falcon_context_init,

		.fini = _nouveau_falcon_context_fini,

		.rd32 = _nouveau_falcon_context_rd32,

		.wr32 = _nouveau_falcon_context_wr32,

	},

};
@@ -66,6 +61,21 @@ nv98_ppp_cclass = { 
 * PPPP engine/subdev functions

 ******************************************************************************/



static int

nv98_ppp_init(struct nouveau_object *object)

{

	struct nv98_ppp_priv *priv = (void *)object;

	int ret;



	ret = nouveau_falcon_init(&priv->base);

	if (ret)

		return ret;



	nv_wr32(priv, 0x086010, 0x0000ffd2);

	nv_wr32(priv, 0x08601c, 0x0000fff2);

	return 0;

}



static int

nv98_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,

	      struct nouveau_oclass *oclass, void *data, u32 size,
@@ -74,7 +84,7 @@ nv98_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 
	struct nv98_ppp_priv *priv;

	int ret;



	ret = nouveau_engine_create(parent, engine, oclass, true,

	ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,

				    "PPPP", "ppp", &priv);

	*pobject = nv_object(priv);

	if (ret)
@@ -91,8 +101,10 @@ nv98_ppp_oclass = { 
	.handle = NV_ENGINE(PPP, 0x98),

	.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = nv98_ppp_ctor,

		.dtor = _nouveau_engine_dtor,

		.init = _nouveau_engine_init,

		.fini = _nouveau_engine_fini,

		.dtor = _nouveau_falcon_dtor,

		.init = nv98_ppp_init,

		.fini = _nouveau_falcon_fini,

		.rd32 = _nouveau_falcon_rd32,

		.wr32 = _nouveau_falcon_wr32,

	},

};

drivers/gpu/drm/nouveau/core/engine/vp/nv98.c

+32 −15
Original line number Diff line number Diff line
@@ -19,16 +19,14 @@ 
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs

 * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin

 */



#include <core/engctx.h>

#include <core/class.h>



#include <engine/falcon.h>

#include <engine/vp.h>



struct nv98_vp_priv {

	struct nouveau_engine base;

	struct nouveau_falcon base;

};



/*******************************************************************************
@@ -37,6 +35,8 @@ struct nv98_vp_priv { 


static struct nouveau_oclass

nv98_vp_sclass[] = {

	{ 0x88b2, &nouveau_object_ofuncs },

	{ 0x85b2, &nouveau_object_ofuncs },

	{},

};
@@ -48,12 +48,12 @@ static struct nouveau_oclass 
nv98_vp_cclass = {

	.handle = NV_ENGCTX(VP, 0x98),

	.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = _nouveau_engctx_ctor,

		.dtor = _nouveau_engctx_dtor,

		.init = _nouveau_engctx_init,

		.fini = _nouveau_engctx_fini,

		.rd32 = _nouveau_engctx_rd32,

		.wr32 = _nouveau_engctx_wr32,

		.ctor = _nouveau_falcon_context_ctor,

		.dtor = _nouveau_falcon_context_dtor,

		.init = _nouveau_falcon_context_init,

		.fini = _nouveau_falcon_context_fini,

		.rd32 = _nouveau_falcon_context_rd32,

		.wr32 = _nouveau_falcon_context_wr32,

	},

};
@@ -61,6 +61,21 @@ nv98_vp_cclass = { 
 * PVP engine/subdev functions

 ******************************************************************************/



static int

nv98_vp_init(struct nouveau_object *object)

{

	struct nv98_vp_priv *priv = (void *)object;

	int ret;



	ret = nouveau_falcon_init(&priv->base);

	if (ret)

		return ret;



	nv_wr32(priv, 0x085010, 0x0000ffd2);

	nv_wr32(priv, 0x08501c, 0x0000fff2);

	return 0;

}



static int

nv98_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,

	     struct nouveau_oclass *oclass, void *data, u32 size,
@@ -69,7 +84,7 @@ nv98_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 
	struct nv98_vp_priv *priv;

	int ret;



	ret = nouveau_engine_create(parent, engine, oclass, true,

	ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true,

				    "PVP", "vp", &priv);

	*pobject = nv_object(priv);

	if (ret)
@@ -86,8 +101,10 @@ nv98_vp_oclass = { 
	.handle = NV_ENGINE(VP, 0x98),

	.ofuncs = &(struct nouveau_ofuncs) {

		.ctor = nv98_vp_ctor,

		.dtor = _nouveau_engine_dtor,

		.init = _nouveau_engine_init,

		.fini = _nouveau_engine_fini,

		.dtor = _nouveau_falcon_dtor,

		.init = nv98_vp_init,

		.fini = _nouveau_falcon_fini,

		.rd32 = _nouveau_falcon_rd32,

		.wr32 = _nouveau_falcon_wr32,

	},

};

drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c

+2 −1
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ nv98_mc_intr[] = { 
	{ 0x00001000, NVDEV_ENGINE_GR },

	{ 0x00004000, NVDEV_ENGINE_CRYPT },	/* NV84:NVA3 */

	{ 0x00008000, NVDEV_ENGINE_BSP },

	{ 0x00020000, NVDEV_ENGINE_VP },

	{ 0x00080000, NVDEV_SUBDEV_THERM },	/* NVA3:NVC0 */

	{ 0x00100000, NVDEV_SUBDEV_TIMER },

	{ 0x00200000, NVDEV_SUBDEV_GPIO },
@@ -42,7 +43,7 @@ nv98_mc_intr[] = { 
	{ 0x04000000, NVDEV_ENGINE_DISP },

	{ 0x10000000, NVDEV_SUBDEV_BUS },

	{ 0x80000000, NVDEV_ENGINE_SW },

	{ 0x0040d101, NVDEV_SUBDEV_FB },

	{ 0x0042d101, NVDEV_SUBDEV_FB },

	{},

};