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Commit ee80f7c7 authored by Steven J. Hill's avatar Steven J. Hill Committed by Ralf Baechle
Browse files

MIPS: Add detection of DSP ASE Revision 2. 



[ralf@linux-mips.org: This patch really only detects the ASE and passes its
existence on to userland via /proc/cpuinfo.  The DSP ASE Rev 2. adds new
resources but no resources that would need management by the kernel.]

Signed-off-by: default avatarSteven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4165/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent f59a2d22

arch/mips/include/asm/cpu-features.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -171,6 +171,10 @@ 
#define cpu_has_dsp		(cpu_data[0].ases & MIPS_ASE_DSP)

#define cpu_has_dsp		(cpu_data[0].ases & MIPS_ASE_DSP)

#endif

#endif





#ifndef cpu_has_dsp2

#define cpu_has_dsp2		(cpu_data[0].ases & MIPS_ASE_DSP2P)

#endif



#ifndef cpu_has_mipsmt

#ifndef cpu_has_mipsmt

#define cpu_has_mipsmt		(cpu_data[0].ases & MIPS_ASE_MIPSMT)

#define cpu_has_mipsmt		(cpu_data[0].ases & MIPS_ASE_MIPSMT)

#endif

#endif

arch/mips/include/asm/cpu.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -332,6 +332,7 @@ enum cpu_type_enum { 
#define MIPS_ASE_SMARTMIPS	0x00000008 /* SmartMIPS */

#define MIPS_ASE_SMARTMIPS	0x00000008 /* SmartMIPS */

#define MIPS_ASE_DSP		0x00000010 /* Signal Processing ASE */

#define MIPS_ASE_DSP		0x00000010 /* Signal Processing ASE */

#define MIPS_ASE_MIPSMT		0x00000020 /* CPU supports MIPS MT */

#define MIPS_ASE_MIPSMT		0x00000020 /* CPU supports MIPS MT */

#define MIPS_ASE_DSP2P		0x00000040 /* Signal Processing ASE Rev 2 */









#endif /* _ASM_CPU_H */
 
#endif /* _ASM_CPU_H */

arch/mips/include/asm/mipsregs.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -592,6 +592,7 @@ 
#define MIPS_CONF3_VEIC		(_ULCAST_(1) <<  6)

#define MIPS_CONF3_VEIC		(_ULCAST_(1) <<  6)

#define MIPS_CONF3_LPA		(_ULCAST_(1) <<  7)

#define MIPS_CONF3_LPA		(_ULCAST_(1) <<  7)

#define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)

#define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)

#define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)

#define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)

#define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)

#define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)

#define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)

arch/mips/kernel/cpu-probe.c

+4 −2
Original line number Original line Diff line number Diff line
@@ -142,7 +142,7 @@ int __cpuinitdata mips_dsp_disabled; 




static int __init dsp_disable(char *s)

static int __init dsp_disable(char *s)

{

{

	cpu_data[0].ases &= ~MIPS_ASE_DSP;

	cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);

	mips_dsp_disabled = 1;

	mips_dsp_disabled = 1;





	return 1;

	return 1;
@@ -429,6 +429,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) 
		c->options |= MIPS_CPU_RIXI;

		c->options |= MIPS_CPU_RIXI;

	if (config3 & MIPS_CONF3_DSP)

	if (config3 & MIPS_CONF3_DSP)

		c->ases |= MIPS_ASE_DSP;

		c->ases |= MIPS_ASE_DSP;

	if (config3 & MIPS_CONF3_DSP2P)

		c->ases |= MIPS_ASE_DSP2P;

	if (config3 & MIPS_CONF3_VINT)

	if (config3 & MIPS_CONF3_VINT)

		c->options |= MIPS_CPU_VINT;

		c->options |= MIPS_CPU_VINT;

	if (config3 & MIPS_CONF3_VEIC)

	if (config3 & MIPS_CONF3_VEIC)
@@ -1180,7 +1182,7 @@ __cpuinit void cpu_probe(void) 
		c->options &= ~MIPS_CPU_FPU;

		c->options &= ~MIPS_CPU_FPU;





	if (mips_dsp_disabled)

	if (mips_dsp_disabled)

		c->ases &= ~MIPS_ASE_DSP;

		c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);





	if (c->options & MIPS_CPU_FPU) {

	if (c->options & MIPS_CPU_FPU) {

		c->fpu_id = cpu_get_fpu_id();

		c->fpu_id = cpu_get_fpu_id();

arch/mips/kernel/proc.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -70,6 +70,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) 
		      cpu_has_mips3d ? " mips3d" : "",

		      cpu_has_mips3d ? " mips3d" : "",

		      cpu_has_smartmips ? " smartmips" : "",

		      cpu_has_smartmips ? " smartmips" : "",

		      cpu_has_dsp ? " dsp" : "",

		      cpu_has_dsp ? " dsp" : "",

		      cpu_has_dsp2 ? " dsp2" : "",

		      cpu_has_mipsmt ? " mt" : ""

		      cpu_has_mipsmt ? " mt" : ""

		);

		);

	seq_printf(m, "shadow register sets\t: %d\n",

	seq_printf(m, "shadow register sets\t: %d\n",