Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

- OMAP5 EVM : Evaluation Module

  compatible = "ti,omap5-evm", "ti,omap5"

- AM43x EPOS EVM

  compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"

For various board the "board" node may contain specific properties

that pertain to this particular board, such as board-specific GPIOs.

Required root node property: src

- Nomadik System and reset controller used for basic chip control, clock

  and reset line control.

- compatible: must be "stericsson,nomadik,src"

Boards with the Nomadik SoC include:

S8815 "MiniKit" manufactured by Calao Systems:

Device tree bindings for i.MX Wireless External Interface Module (WEIM)

The term "wireless" does not imply that the WEIM is literally an interface

without wires. It simply means that this module was originally designed for

wireless and mobile applications that use low-power technology.

The actual devices are instantiated from the child nodes of a WEIM node.

Required properties:

 - compatible:		Should be set to "fsl,imx6q-weim"

 - reg:			A resource specifier for the register space

			(see the example below)

 - clocks:		the clock, see the example below.

 - #address-cells:	Must be set to 2 to allow memory address translation

 - #size-cells:		Must be set to 1 to allow CS address passing

 - ranges:		Must be set up to reflect the memory layout with four

			integer values for each chip-select line in use:

			   <cs-number> 0 <physical address of mapping> <size>

Timing property for child nodes. It is mandatory, not optional.

 - fsl,weim-cs-timing:	The timing array, contains 6 timing values for the

			child node. We can get the CS index from the child

			node's "reg" property. This property contains the values

			for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,

			EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.

Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:

	weim: weim@021b8000 {

		compatible = "fsl,imx6q-weim";

		reg = <0x021b8000 0x4000>;

		clocks = <&clks 196>;

		#address-cells = <2>;

		#size-cells = <1>;

		ranges = <0 0 0x08000000 0x08000000>;

		nor@0,0 {

			compatible = "cfi-flash";

			reg = <0 0 0x02000000>;

			#address-cells = <1>;

			#size-cells = <1>;

			bank-width = <2>;

			fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000

					0x0000c000 0x1404a38e 0x00000000>;

		};

	};

	"altr,socfpga-pll-clock" - for a PLL clock

	"altr,socfpga-perip-clock" - The peripheral clock divided from the

		PLL clock.

	"altr,socfpga-gate-clk" - Clocks that directly feed peripherals and

		can get gated.

- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.

- clocks : shall be the input parent clock phandle for the clock. This is

	either an oscillator or a pll output.

Optional properties:

- fixed-divider : If clocks have a fixed divider value, use this property.

- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register

        and the bit index.

- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,

        and width.

  sclk_spi0_isp       174     Exynos4x12

  sclk_spi1_isp       175     Exynos4x12

  sclk_uart_isp       176     Exynos4x12

  sclk_fimg2d         177

	      [Peripheral Clock Gates]

  smmu_mfcl           274

  smmu_mfcr           275

  g3d                 276

  g2d                 277     Exynos4210

  g2d                 277

  rotator             278     Exynos4210

  mdma                279     Exynos4210

  smmu_g2d            280     Exynos4210