Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ee1466e0 authored by Vladimir Kondratiev's avatar Vladimir Kondratiev Committed by Ian Maund
Browse files

wil6210: use inline functions for register access 



Replace macros like "R", "W", "S", "C", defined multiple times,
with inline functions "wil_[rwsc]".

Use "readl" and "writel" instead of "ioread32" and "iowrite32"
since it is granted that memory transactions are used,
not port ones like IN/OUT

Change-Id: I047eecdbe4766cc66f19d8a445c3fb0ee0a904c7
Signed-off-by: default avatarVladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>
Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
Git-commit: b9eeb512496f1b1b5a6e0748c947277d95003af5
Git-repo: https://github.com/kvalo/ath.git


Signed-off-by: default avatarHamad Kadmany <hkadmany@codeaurora.org>
parent 155452d8

drivers/net/wireless/ath/wil6210/debugfs.c

+4 −4
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ static void wil_print_vring(struct seq_file *s, struct wil6210_priv *wil, 
	seq_printf(s, "  swhead = %d\n", vring->swhead);

	seq_printf(s, "  hwtail = [0x%08x] -> ", vring->hwtail);

	if (x) {

		v = ioread32(x);

		v = readl(x);

		seq_printf(s, "0x%08x = %d\n", v, v);

	} else {

		seq_puts(s, "???\n");
@@ -268,7 +268,7 @@ static const struct file_operations fops_mbox = { 


static int wil_debugfs_iomem_x32_set(void *data, u64 val)

{

	iowrite32(val, (void __iomem *)data);

	writel(val, (void __iomem *)data);

	wmb(); /* make sure write propagated to HW */



	return 0;
@@ -276,7 +276,7 @@ static int wil_debugfs_iomem_x32_set(void *data, u64 val) 


static int wil_debugfs_iomem_x32_get(void *data, u64 *val)

{

	*val = ioread32((void __iomem *)data);

	*val = readl((void __iomem *)data);



	return 0;

}
@@ -477,7 +477,7 @@ static int wil_memread_debugfs_show(struct seq_file *s, void *data) 
	void __iomem *a = wmi_buffer(wil, cpu_to_le32(mem_addr));



	if (a)

		seq_printf(s, "[0x%08x] = 0x%08x\n", mem_addr, ioread32(a));

		seq_printf(s, "[0x%08x] = 0x%08x\n", mem_addr, readl(a));

	else

		seq_printf(s, "[0x%08x] = INVALID\n", mem_addr);

drivers/net/wireless/ath/wil6210/ethtool.c

+4 −10
Original line number Diff line number Diff line
@@ -50,19 +50,13 @@ static int wil_ethtoolops_get_coalesce(struct net_device *ndev, 


	wil_dbg_misc(wil, "%s()\n", __func__);



	tx_itr_en = ioread32(wil->csr +

			     HOSTADDR(RGF_DMA_ITR_TX_CNT_CTL));

	tx_itr_en = wil_r(wil, RGF_DMA_ITR_TX_CNT_CTL);

	if (tx_itr_en & BIT_DMA_ITR_TX_CNT_CTL_EN)

		tx_itr_val =

			ioread32(wil->csr +

				 HOSTADDR(RGF_DMA_ITR_TX_CNT_TRSH));

		tx_itr_val = wil_r(wil, RGF_DMA_ITR_TX_CNT_TRSH);



	rx_itr_en = ioread32(wil->csr +

			     HOSTADDR(RGF_DMA_ITR_RX_CNT_CTL));

	rx_itr_en = wil_r(wil, RGF_DMA_ITR_RX_CNT_CTL);

	if (rx_itr_en & BIT_DMA_ITR_RX_CNT_CTL_EN)

		rx_itr_val =

			ioread32(wil->csr +

				 HOSTADDR(RGF_DMA_ITR_RX_CNT_TRSH));

		rx_itr_val = wil_r(wil, RGF_DMA_ITR_RX_CNT_TRSH);



	cp->tx_coalesce_usecs = tx_itr_val;

	cp->rx_coalesce_usecs = rx_itr_val;

drivers/net/wireless/ath/wil6210/fw.c

+0 −10
Original line number Diff line number Diff line
@@ -22,16 +22,6 @@ 
MODULE_FIRMWARE(WIL_FW_NAME);

MODULE_FIRMWARE(WIL_FW2_NAME);



/* target operations */

/* register read */

#define R(a) ioread32(wil->csr + HOSTADDR(a))

/* register write. wmb() to make sure it is completed */

#define W(a, v) do { iowrite32(v, wil->csr + HOSTADDR(a)); wmb(); } while (0)

/* register set = read, OR, write */

#define S(a, v) W(a, R(a) | v)

/* register clear = read, AND with inverted, write */

#define C(a, v) W(a, R(a) & ~v)



static

void wil_memset_toio_32(volatile void __iomem *dst, u32 val,

			size_t count)

drivers/net/wireless/ath/wil6210/fw_inc.c

+8 −8
Original line number Diff line number Diff line
@@ -221,12 +221,12 @@ static int fw_handle_direct_write(struct wil6210_priv *wil, const void *data, 


		FW_ADDR_CHECK(dst, block[i].addr, "address");



		x = ioread32(dst);

		x = readl(dst);

		y = (x & m) | (v & ~m);

		wil_dbg_fw(wil, "write [0x%08x] <== 0x%08x "

			   "(old 0x%08x val 0x%08x mask 0x%08x)\n",

			   le32_to_cpu(block[i].addr), y, x, v, m);

		iowrite32(y, dst);

		writel(y, dst);

		wmb(); /* finish before processing next record */

	}
@@ -239,18 +239,18 @@ static int gw_write(struct wil6210_priv *wil, void __iomem *gwa_addr, 
{

	unsigned delay = 0;



	iowrite32(a, gwa_addr);

	iowrite32(gw_cmd, gwa_cmd);

	writel(a, gwa_addr);

	writel(gw_cmd, gwa_cmd);

	wmb(); /* finish before activate gw */



	iowrite32(WIL_FW_GW_CTL_RUN, gwa_ctl); /* activate gw */

	writel(WIL_FW_GW_CTL_RUN, gwa_ctl); /* activate gw */

	do {

		udelay(1); /* typical time is few usec */

		if (delay++ > 100) {

			wil_err_fw(wil, "gw timeout\n");

			return -EINVAL;

		}

	} while (ioread32(gwa_ctl) & WIL_FW_GW_CTL_BUSY); /* gw done? */

	} while (readl(gwa_ctl) & WIL_FW_GW_CTL_BUSY); /* gw done? */



	return 0;

}
@@ -305,7 +305,7 @@ static int fw_handle_gateway_data(struct wil6210_priv *wil, const void *data, 
		wil_dbg_fw(wil, "  gw write[%3d] [0x%08x] <== 0x%08x\n",

			   i, a, v);



		iowrite32(v, gwa_val);

		writel(v, gwa_val);

		rc = gw_write(wil, gwa_addr, gwa_cmd, gwa_ctl, gw_cmd, a);

		if (rc)

			return rc;
@@ -372,7 +372,7 @@ static int fw_handle_gateway_data4(struct wil6210_priv *wil, const void *data, 
				sizeof(v), false);



		for (k = 0; k < ARRAY_SIZE(block->value); k++)

			iowrite32(v[k], gwa_val[k]);

			writel(v[k], gwa_val[k]);

		rc = gw_write(wil, gwa_addr, gwa_cmd, gwa_ctl, gw_cmd, a);

		if (rc)

			return rc;

drivers/net/wireless/ath/wil6210/interrupt.c

+47 −63
Original line number Diff line number Diff line
@@ -61,13 +61,13 @@ static inline void wil_icr_clear(u32 x, void __iomem *addr) 


static inline void wil_icr_clear(u32 x, void __iomem *addr)

{

	iowrite32(x, addr);

	writel(x, addr);

}

#endif /* defined(CONFIG_WIL6210_ISR_COR) */



static inline u32 wil_ioread32_and_clear(void __iomem *addr)

{

	u32 x = ioread32(addr);

	u32 x = readl(addr);



	wil_icr_clear(x, addr);
@@ -76,54 +76,47 @@ static inline u32 wil_ioread32_and_clear(void __iomem *addr) 


static void wil6210_mask_irq_tx(struct wil6210_priv *wil)

{

	iowrite32(WIL6210_IRQ_DISABLE, wil->csr +

		  HOSTADDR(RGF_DMA_EP_TX_ICR) +

		  offsetof(struct RGF_ICR, IMS));

	wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS),

	      WIL6210_IRQ_DISABLE);

}



static void wil6210_mask_irq_rx(struct wil6210_priv *wil)

{

	iowrite32(WIL6210_IRQ_DISABLE, wil->csr +

		  HOSTADDR(RGF_DMA_EP_RX_ICR) +

		  offsetof(struct RGF_ICR, IMS));

	wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS),

	      WIL6210_IRQ_DISABLE);

}



static void wil6210_mask_irq_misc(struct wil6210_priv *wil)

{

	iowrite32(WIL6210_IRQ_DISABLE, wil->csr +

		  HOSTADDR(RGF_DMA_EP_MISC_ICR) +

		  offsetof(struct RGF_ICR, IMS));

	wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),

	      WIL6210_IRQ_DISABLE);

}



static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)

{

	wil_dbg_irq(wil, "%s()\n", __func__);



	iowrite32(WIL6210_IRQ_DISABLE, wil->csr +

		  HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));

	wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE);



	clear_bit(wil_status_irqen, wil->status);

}



void wil6210_unmask_irq_tx(struct wil6210_priv *wil)

{

	iowrite32(WIL6210_IMC_TX, wil->csr +

		  HOSTADDR(RGF_DMA_EP_TX_ICR) +

		  offsetof(struct RGF_ICR, IMC));

	wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC),

	      WIL6210_IMC_TX);

}



void wil6210_unmask_irq_rx(struct wil6210_priv *wil)

{

	iowrite32(WIL6210_IMC_RX, wil->csr +

		  HOSTADDR(RGF_DMA_EP_RX_ICR) +

		  offsetof(struct RGF_ICR, IMC));

	wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC),

	      WIL6210_IMC_RX);

}



static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)

{

	iowrite32(WIL6210_IMC_MISC, wil->csr +

		  HOSTADDR(RGF_DMA_EP_MISC_ICR) +

		  offsetof(struct RGF_ICR, IMC));

	wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),

	      WIL6210_IMC_MISC);

}



static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
@@ -132,8 +125,7 @@ static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil) 


	set_bit(wil_status_irqen, wil->status);



	iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +

		  HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));

	wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK);

}



void wil_mask_irq(struct wil6210_priv *wil)
@@ -150,12 +142,12 @@ void wil_unmask_irq(struct wil6210_priv *wil) 
{

	wil_dbg_irq(wil, "%s()\n", __func__);



	iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +

		  offsetof(struct RGF_ICR, ICC));

	iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +

		  offsetof(struct RGF_ICR, ICC));

	iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +

		  offsetof(struct RGF_ICR, ICC));

	wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC),

	      WIL_ICR_ICC_VALUE);

	wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC),

	      WIL_ICR_ICC_VALUE);

	wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC),

	      WIL_ICR_ICC_VALUE);



	wil6210_unmask_irq_pseudo(wil);

	wil6210_unmask_irq_tx(wil);
@@ -163,9 +155,6 @@ void wil_unmask_irq(struct wil6210_priv *wil) 
	wil6210_unmask_irq_misc(wil);

}



/* target write operation */

#define W(a, v) do { iowrite32(v, wil->csr + HOSTADDR(a)); wmb(); } while (0)



void wil_configure_interrupt_moderation(struct wil6210_priv *wil)

{

	wil_dbg_irq(wil, "%s()\n", __func__);
@@ -177,44 +166,42 @@ void wil_configure_interrupt_moderation(struct wil6210_priv *wil) 
		return;



	/* Disable and clear tx counter before (re)configuration */

	W(RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR);

	W(RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration);

	wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR);

	wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration);

	wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n",

		 wil->tx_max_burst_duration);

	/* Configure TX max burst duration timer to use usec units */

	W(RGF_DMA_ITR_TX_CNT_CTL,

	wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL,

	      BIT_DMA_ITR_TX_CNT_CTL_EN | BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL);



	/* Disable and clear tx idle counter before (re)configuration */

	W(RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR);

	W(RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout);

	wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR);

	wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout);

	wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n",

		 wil->tx_interframe_timeout);

	/* Configure TX max burst duration timer to use usec units */

	W(RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN |

	wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN |

	      BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL);



	/* Disable and clear rx counter before (re)configuration */

	W(RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR);

	W(RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration);

	wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR);

	wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration);

	wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n",

		 wil->rx_max_burst_duration);

	/* Configure TX max burst duration timer to use usec units */

	W(RGF_DMA_ITR_RX_CNT_CTL,

	wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL,

	      BIT_DMA_ITR_RX_CNT_CTL_EN | BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL);



	/* Disable and clear rx idle counter before (re)configuration */

	W(RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR);

	W(RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout);

	wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR);

	wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout);

	wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n",

		 wil->rx_interframe_timeout);

	/* Configure TX max burst duration timer to use usec units */

	W(RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN |

	wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN |

	      BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL);

}



#undef W



static irqreturn_t wil6210_irq_rx(int irq, void *cookie)

{

	struct wil6210_priv *wil = cookie;
@@ -452,8 +439,7 @@ static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause) 
		u32 icr_rx = wil_ioread32_and_clear(wil->csr +

				HOSTADDR(RGF_DMA_EP_RX_ICR) +

				offsetof(struct RGF_ICR, ICR));

		u32 imv_rx = ioread32(wil->csr +

				HOSTADDR(RGF_DMA_EP_RX_ICR) +

		u32 imv_rx = wil_r(wil, RGF_DMA_EP_RX_ICR +

				   offsetof(struct RGF_ICR, IMV));

		u32 icm_tx = wil_ioread32_and_clear(wil->csr +

				HOSTADDR(RGF_DMA_EP_TX_ICR) +
@@ -461,8 +447,7 @@ static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause) 
		u32 icr_tx = wil_ioread32_and_clear(wil->csr +

				HOSTADDR(RGF_DMA_EP_TX_ICR) +

				offsetof(struct RGF_ICR, ICR));

		u32 imv_tx = ioread32(wil->csr +

				HOSTADDR(RGF_DMA_EP_TX_ICR) +

		u32 imv_tx = wil_r(wil, RGF_DMA_EP_TX_ICR +

				   offsetof(struct RGF_ICR, IMV));

		u32 icm_misc = wil_ioread32_and_clear(wil->csr +

				HOSTADDR(RGF_DMA_EP_MISC_ICR) +
@@ -470,8 +455,7 @@ static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause) 
		u32 icr_misc = wil_ioread32_and_clear(wil->csr +

				HOSTADDR(RGF_DMA_EP_MISC_ICR) +

				offsetof(struct RGF_ICR, ICR));

		u32 imv_misc = ioread32(wil->csr +

				HOSTADDR(RGF_DMA_EP_MISC_ICR) +

		u32 imv_misc = wil_r(wil, RGF_DMA_EP_MISC_ICR +

				     offsetof(struct RGF_ICR, IMV));

		wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"

				"Rx   icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
@@ -492,7 +476,7 @@ static irqreturn_t wil6210_hardirq(int irq, void *cookie) 
{

	irqreturn_t rc = IRQ_HANDLED;

	struct wil6210_priv *wil = cookie;

	u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));

	u32 pseudo_cause = wil_r(wil, RGF_DMA_PSEUDO_CAUSE);



	/**

	 * pseudo_cause is Clear-On-Read, no need to ACK
@@ -544,9 +528,9 @@ static irqreturn_t wil6210_hardirq(int irq, void *cookie) 
/* can't use wil_ioread32_and_clear because ICC value is not set yet */

static inline void wil_clear32(void __iomem *addr)

{

	u32 x = ioread32(addr);

	u32 x = readl(addr);



	iowrite32(x, addr);

	writel(x, addr);

}



void wil6210_clear_irq(struct wil6210_priv *wil)