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Commit edfd0baf authored by Taniya Das's avatar Taniya Das
Browse files

clk: msm: clock-gcc: Update rcg source for usb30_utmi clock



The source to generate 60MHz has been updated to gpll6_div2, so update the
same.

Change-Id: I4eda86771bf6fb665475ba4260f8c78d627a2e78
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 6d22be2e
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+3 −2
Original line number Diff line number Diff line
@@ -219,6 +219,7 @@ DEFINE_EXT_CLK(gpll6_main_clk_src, &gpll6_clk_src.c);
DEFINE_EXT_CLK(gpll6_main_div2_clk_src, &gpll6_clk_src.c);
DEFINE_EXT_CLK(gpll6_main_div2_gfx_clk_src, &gpll6_clk_src.c);
DEFINE_EXT_CLK(gpll6_main_gfx_clk_src, &gpll6_clk_src.c);
DEFINE_EXT_CLK(gpll6_main_div2_mock_clk_src, &gpll6_clk_src.c);
DEFINE_EXT_CLK(gpll6_out_aux_clk_src, &gpll6_clk_src.c);

DEFINE_EXT_CLK(ext_pclk0_clk_src, NULL);
@@ -1628,7 +1629,7 @@ static struct rcg_clk sdcc2_apps_clk_src = {

static struct clk_freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
	F(  19200000,                       xo,    1,    0,     0),
	F(  60000000,     gpll6_main,    6,    1,     3),
	F(  60000000,     gpll6_main_div2_mock,    9,    1,     1),
	F_END
};

+2 −0
Original line number Diff line number Diff line
@@ -510,6 +510,8 @@
#define gpll6_src_val			2
#define gpll6_main_gfx_src_val		3   /* gfx3d_clk_src */

#define gpll6_main_div2_mock_src_val    2   /* usb30_mock_utmi_clk_src */

#define gpll6_main_div2_src_val		5   /* mclk0_clk_src mclk1_clk_src
					       mclk2_clk_src mclk3_clk_src */
#define gpll6_main_div2_gfx_src_val	6   /* gfx3d_clk_src */