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Commit edabd38e authored by Saeed Bishara's avatar Saeed Bishara Committed by Nicolas Pitre
Browse files

ARM: add base support for Marvell Dove SoC 



The Marvell Dove (88AP510) is a high-performance, highly integrated,
low power SoC with high-end ARM-compatible processor (known as PJ4),
graphics processing unit, high-definition video decoding acceleration
hardware, and a broad range of peripherals.

Signed-off-by: default avatarLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: default avatarSaeed Bishara <saeed@marvell.com>
Signed-off-by: default avatarNicolas Pitre <nico@marvell.com>
parent 8d27b2f7

arch/arm/Kconfig

+13 −0
Original line number Diff line number Diff line
@@ -433,6 +433,17 @@ config ARCH_L7200 
	  If you have any questions or comments about the Linux kernel port

	  to this board, send e-mail to <sjhill@cotw.com>.



config ARCH_DOVE

	bool "Marvell Dove"

	select PCI

	select GENERIC_GPIO

	select ARCH_REQUIRE_GPIOLIB

	select GENERIC_TIME

	select GENERIC_CLOCKEVENTS

	select PLAT_ORION

	help

	  Support for the Marvell Dove SoC 88AP510



config ARCH_KIRKWOOD

	bool "Marvell Kirkwood"

	select CPU_FEROCEON
@@ -747,6 +758,8 @@ source "arch/arm/mach-orion5x/Kconfig" 


source "arch/arm/mach-kirkwood/Kconfig"



source "arch/arm/mach-dove/Kconfig"



source "arch/arm/plat-s3c24xx/Kconfig"

source "arch/arm/plat-s3c64xx/Kconfig"

source "arch/arm/plat-s3c/Kconfig"

arch/arm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -122,6 +122,7 @@ machine-$(CONFIG_ARCH_AT91) := at91 
machine-$(CONFIG_ARCH_BCMRING)		:= bcmring

machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x

machine-$(CONFIG_ARCH_DAVINCI)		:= davinci

machine-$(CONFIG_ARCH_DOVE)		:= dove

machine-$(CONFIG_ARCH_EBSA110)		:= ebsa110

machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx

machine-$(CONFIG_ARCH_GEMINI)		:= gemini

arch/arm/boot/compressed/head.S

+6 −0
Original line number Diff line number Diff line
@@ -743,6 +743,12 @@ proc_types: 
		W(b)	__armv4_mmu_cache_off

		W(b)	__armv6_mmu_cache_flush



		.word	0x560f5810		@ Marvell PJ4 ARMv6

		.word	0xff0ffff0

		W(b)	__armv4_mmu_cache_on

		W(b)	__armv4_mmu_cache_off

		W(b)	__armv6_mmu_cache_flush



		.word	0x000f0000		@ new CPU Id

		.word	0x000f0000

		W(b)	__armv7_mmu_cache_on