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Commit ed85703d authored by Sivan Reinstein's avatar Sivan Reinstein Committed by Rama Krishna Phani A
Browse files

msm: ipa: revert I90ed686a1697f600cdc69e43e8c6dd8032034293 



Need the WA for Q6 pipe reset during SSR.

Change-Id: Ie8726be862fda2c81fee1119659455f3ffe4f2de
Acked-by: default avatarChaitanya Pratapa <cpratapa@qti.qualcomm.com>
Acked-by: default avatarDavid Arinzon <darinzon@qti.qualcomm.com>
Signed-off-by: default avatarRavinder Konka <rkonka@codeaurora.org>
Signed-off-by: default avatarSivan Reinstein <sivanr@codeaurora.org>
parent 8ccf1868

drivers/platform/msm/ipa/ipa_v2/ipa.c

+17 −19
Original line number Diff line number Diff line
@@ -1642,8 +1642,6 @@ int ipa_q6_cleanup(void) 
		BUG();

	}



	/* This workaround is required for pre IPA2.6HW MSMs */

	if (ipa_ctx->ipa_hw_type < IPA_HW_v2_5) {

	/*

	 * Q6 relies on the AP to reset all Q6 IPA pipes.

	 * In case the uC is not loaded, or upon any failure in the
@@ -1661,7 +1659,7 @@ int ipa_q6_cleanup(void) 
			if (res)

				BUG();

		}

	}



	ipa_ctx->q6_proxy_clk_vote_valid = true;

	return 0;

}

drivers/platform/msm/ipa/ipa_v2/ipa_uc.c

+1 −1
Original line number Diff line number Diff line
@@ -715,7 +715,7 @@ int ipa_uc_reset_pipe(enum ipa_client_type ipa_client) 
	       IPA_CLIENT_IS_PROD(ipa_client) ? "CONS" : "PROD", ep_idx);



	ret = ipa_uc_send_cmd(cmd.raw32b, IPA_CPU_2_HW_CMD_RESET_PIPE, 0,

			      false, 10*HZ);

			      true, 10*HZ);



	return ret;

}