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Commit ecddd18c authored by Subbaraman Narayanamurthy's avatar Subbaraman Narayanamurthy Committed by Gerrit - the friendly Code Review server
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power: qpnp-fg: allow reconfiguration of thermistor control setting 



Currently, we configure the FG SRAM register 0x4AF only if the
qcom,sw-rbias-control property is specified through device tree.
However, if that property is not specified for a device anymore
where it was specified before, previous configuration would be
retained unless there is a dVdd reset. Reconfigure the register
0x4AF to allow the default thermistor settings in such cases.

CRs-Fixed: 880044
Change-Id: Ic9bbea3d68968c39bf9b66532278178de9104b24
Signed-off-by: default avatarSubbaraman Narayanamurthy <subbaram@codeaurora.org>
parent 9f5234bb

drivers/power/qpnp-fg.c

+18 −2
Original line number Diff line number Diff line
@@ -2001,8 +2001,13 @@ out: 


#define BATT_TEMP_OFFSET	3

#define BATT_TEMP_CNTRL_MASK	0x17

#define BATT_TEMP_ON		0x16

#define BATT_TEMP_OFF		0x01

#define DISABLE_THERM_BIT	BIT(0)

#define TEMP_SENSE_ALWAYS_BIT	BIT(1)

#define TEMP_SENSE_CHARGE_BIT	BIT(2)

#define FORCE_RBIAS_ON_BIT	BIT(4)

#define BATT_TEMP_OFF		DISABLE_THERM_BIT

#define BATT_TEMP_ON		(FORCE_RBIAS_ON_BIT | TEMP_SENSE_ALWAYS_BIT | \

				TEMP_SENSE_CHARGE_BIT)

#define TEMP_PERIOD_UPDATE_MS		10000

#define TEMP_PERIOD_TIMEOUT_MS		3000

static void update_temp_data(struct work_struct *work)
@@ -5208,6 +5213,17 @@ static int fg_common_hw_init(struct fg_chip *chip) 
			THERMAL_COEFF_OFFSET, 0);

	}



	if (!chip->sw_rbias_ctrl) {

		rc = fg_mem_masked_write(chip, EXTERNAL_SENSE_SELECT,

				BATT_TEMP_CNTRL_MASK,

				TEMP_SENSE_ALWAYS_BIT,

				BATT_TEMP_OFFSET);

		if (rc) {

			pr_err("failed to write BATT_TEMP_OFFSET rc=%d\n", rc);

			return rc;

		}

	}



	return 0;

}